diff --git a/library/SubcircuitLibrary/74ALS10A/74ALS10A-cache.lib b/library/SubcircuitLibrary/74ALS10A/74ALS10A-cache.lib
new file mode 100644
index 000000000..ca4c4883d
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/74ALS10A-cache.lib
@@ -0,0 +1,62 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_NAND
+#
+DEF CMOS_NAND X 0 40 Y Y 1 F N
+F0 "X" -100 -150 60 H V C CNN
+F1 "CMOS_NAND" 0 -50 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -350 300 300 300 N
+P 3 0 1 0 -350 300 -350 -400 300 -400 N
+X in1 1 -550 250 200 R 50 50 1 1 I
+X in2 2 -550 -300 200 R 50 50 1 1 I
+X out 3 800 0 279 L 79 79 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74ALS10A/74ALS10A.cir b/library/SubcircuitLibrary/74ALS10A/74ALS10A.cir
new file mode 100644
index 000000000..ad4151863
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/74ALS10A.cir
@@ -0,0 +1,17 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74ALS10A\74ALS10A.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/30/26 14:55:34
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X3  Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_X3-Pad3_ CMOS_NAND		
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad3_ CMOS_NAND		
+X4  Net-_X3-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad10_ CMOS_NAND		
+X5  Net-_X1-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad11_ CMOS_NAND		
+X2  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_X2-Pad3_ CMOS_NAND		
+X6  Net-_X2-Pad3_ Net-_U1-Pad9_ Net-_U1-Pad12_ CMOS_NAND		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74ALS10A/74ALS10A.cir.out b/library/SubcircuitLibrary/74ALS10A/74ALS10A.cir.out
new file mode 100644
index 000000000..2725a7108
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/74ALS10A.cir.out
@@ -0,0 +1,19 @@
+* c:\fossee\esim\library\subcircuitlibrary\74als10a\74als10a.cir
+
+.include CMOS_NAND.sub
+x3 net-_u1-pad5_ net-_u1-pad6_ net-_x3-pad3_ CMOS_NAND
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad3_ CMOS_NAND
+x4 net-_x3-pad3_ net-_u1-pad7_ net-_u1-pad10_ CMOS_NAND
+x5 net-_x1-pad3_ net-_u1-pad8_ net-_u1-pad11_ CMOS_NAND
+x2 net-_u1-pad3_ net-_u1-pad4_ net-_x2-pad3_ CMOS_NAND
+x6 net-_x2-pad3_ net-_u1-pad9_ net-_u1-pad12_ CMOS_NAND
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74ALS10A/74ALS10A.pro b/library/SubcircuitLibrary/74ALS10A/74ALS10A.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/74ALS10A.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74ALS10A/74ALS10A.sch b/library/SubcircuitLibrary/74ALS10A/74ALS10A.sch
new file mode 100644
index 000000000..21f29e0df
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/74ALS10A.sch
@@ -0,0 +1,261 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74ALS10A_ckt-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CMOS_NAND X3
+U 1 1 697C78FC
+P 4550 1100
+F 0 "X3" H 4450 950 60  0000 C CNN
+F 1 "CMOS_NAND" H 4550 1050 60  0000 C CNN
+F 2 "" H 4550 1100 60  0001 C CNN
+F 3 "" H 4550 1100 60  0001 C CNN
+	1    4550 1100
+	1    0    0    -1  
+$EndComp
+$Comp
+L CMOS_NAND X1
+U 1 1 697C78FD
+P 4450 3600
+F 0 "X1" H 4350 3450 60  0000 C CNN
+F 1 "CMOS_NAND" H 4450 3550 60  0000 C CNN
+F 2 "" H 4450 3600 60  0001 C CNN
+F 3 "" H 4450 3600 60  0001 C CNN
+	1    4450 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L CMOS_NAND X4
+U 1 1 697C78FE
+P 6000 1350
+F 0 "X4" H 5900 1200 60  0000 C CNN
+F 1 "CMOS_NAND" H 6000 1300 60  0000 C CNN
+F 2 "" H 6000 1350 60  0001 C CNN
+F 3 "" H 6000 1350 60  0001 C CNN
+	1    6000 1350
+	1    0    0    -1  
+$EndComp
+$Comp
+L CMOS_NAND X5
+U 1 1 697C78FF
+P 6000 3850
+F 0 "X5" H 5900 3700 60  0000 C CNN
+F 1 "CMOS_NAND" H 6000 3800 60  0000 C CNN
+F 2 "" H 6000 3850 60  0001 C CNN
+F 3 "" H 6000 3850 60  0001 C CNN
+	1    6000 3850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5250 3600 5450 3600
+Wire Wire Line
+	5350 1100 5450 1100
+$Comp
+L CMOS_NAND X2
+U 1 1 697C7907
+P 4500 2400
+F 0 "X2" H 4400 2250 60  0000 C CNN
+F 1 "CMOS_NAND" H 4500 2350 60  0000 C CNN
+F 2 "" H 4500 2400 60  0001 C CNN
+F 3 "" H 4500 2400 60  0001 C CNN
+	1    4500 2400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5300 2400 5500 2400
+$Comp
+L CMOS_NAND X6
+U 1 1 697C7908
+P 6050 2650
+F 0 "X6" H 5950 2500 60  0000 C CNN
+F 1 "CMOS_NAND" H 6050 2600 60  0000 C CNN
+F 2 "" H 6050 2650 60  0001 C CNN
+F 3 "" H 6050 2650 60  0001 C CNN
+	1    6050 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 697C7C4C
+P 3700 2150
+F 0 "U1" H 3750 2250 30  0000 C CNN
+F 1 "PORT" H 3700 2150 30  0000 C CNN
+F 2 "" H 3700 2150 60  0000 C CNN
+F 3 "" H 3700 2150 60  0000 C CNN
+	3    3700 2150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 697C8152
+P 3750 850
+F 0 "U1" H 3800 950 30  0000 C CNN
+F 1 "PORT" H 3750 850 30  0000 C CNN
+F 2 "" H 3750 850 60  0000 C CNN
+F 3 "" H 3750 850 60  0000 C CNN
+	5    3750 850 
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 697C8189
+P 3750 1400
+F 0 "U1" H 3800 1500 30  0000 C CNN
+F 1 "PORT" H 3750 1400 30  0000 C CNN
+F 2 "" H 3750 1400 60  0000 C CNN
+F 3 "" H 3750 1400 60  0000 C CNN
+	6    3750 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 697C81B6
+P 6550 1350
+F 0 "U1" H 6600 1450 30  0000 C CNN
+F 1 "PORT" H 6550 1350 30  0000 C CNN
+F 2 "" H 6550 1350 60  0000 C CNN
+F 3 "" H 6550 1350 60  0000 C CNN
+	10   6550 1350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 697C8543
+P 5200 1650
+F 0 "U1" H 5250 1750 30  0000 C CNN
+F 1 "PORT" H 5200 1650 30  0000 C CNN
+F 2 "" H 5200 1650 60  0000 C CNN
+F 3 "" H 5200 1650 60  0000 C CNN
+	7    5200 1650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 697C856E
+P 3700 2700
+F 0 "U1" H 3750 2800 30  0000 C CNN
+F 1 "PORT" H 3700 2700 30  0000 C CNN
+F 2 "" H 3700 2700 60  0000 C CNN
+F 3 "" H 3700 2700 60  0000 C CNN
+	4    3700 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 697C859B
+P 5250 2950
+F 0 "U1" H 5300 3050 30  0000 C CNN
+F 1 "PORT" H 5250 2950 30  0000 C CNN
+F 2 "" H 5250 2950 60  0000 C CNN
+F 3 "" H 5250 2950 60  0000 C CNN
+	9    5250 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 697C85DA
+P 6600 2650
+F 0 "U1" H 6650 2750 30  0000 C CNN
+F 1 "PORT" H 6600 2650 30  0000 C CNN
+F 2 "" H 6600 2650 60  0000 C CNN
+F 3 "" H 6600 2650 60  0000 C CNN
+	12   6600 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 697C8ABB
+P 3650 3350
+F 0 "U1" H 3700 3450 30  0000 C CNN
+F 1 "PORT" H 3650 3350 30  0000 C CNN
+F 2 "" H 3650 3350 60  0000 C CNN
+F 3 "" H 3650 3350 60  0000 C CNN
+	1    3650 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 697C8AF2
+P 3650 3900
+F 0 "U1" H 3700 4000 30  0000 C CNN
+F 1 "PORT" H 3650 3900 30  0000 C CNN
+F 2 "" H 3650 3900 60  0000 C CNN
+F 3 "" H 3650 3900 60  0000 C CNN
+	2    3650 3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 697C8B2B
+P 5200 4150
+F 0 "U1" H 5250 4250 30  0000 C CNN
+F 1 "PORT" H 5200 4150 30  0000 C CNN
+F 2 "" H 5200 4150 60  0000 C CNN
+F 3 "" H 5200 4150 60  0000 C CNN
+	8    5200 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 697C8B66
+P 6550 3850
+F 0 "U1" H 6600 3950 30  0000 C CNN
+F 1 "PORT" H 6550 3850 30  0000 C CNN
+F 2 "" H 6550 3850 60  0000 C CNN
+F 3 "" H 6550 3850 60  0000 C CNN
+	11   6550 3850
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74ALS10A/74ALS10A.sub b/library/SubcircuitLibrary/74ALS10A/74ALS10A.sub
new file mode 100644
index 000000000..7167f032d
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/74ALS10A.sub
@@ -0,0 +1,13 @@
+* Subcircuit 74ALS10A
+.subckt 74ALS10A net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
+* c:\fossee\esim\library\subcircuitlibrary\74als10a\74als10a.cir
+.include CMOS_NAND.sub
+x3 net-_u1-pad5_ net-_u1-pad6_ net-_x3-pad3_ CMOS_NAND
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad3_ CMOS_NAND
+x4 net-_x3-pad3_ net-_u1-pad7_ net-_u1-pad10_ CMOS_NAND
+x5 net-_x1-pad3_ net-_u1-pad8_ net-_u1-pad11_ CMOS_NAND
+x2 net-_u1-pad3_ net-_u1-pad4_ net-_x2-pad3_ CMOS_NAND
+x6 net-_x2-pad3_ net-_u1-pad9_ net-_u1-pad12_ CMOS_NAND
+* Control Statements
+
+.ends 74ALS10A
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ALS10A/74ALS10A_Previous_Values.xml b/library/SubcircuitLibrary/74ALS10A/74ALS10A_Previous_Values.xml
new file mode 100644
index 000000000..0f4161e5f
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/74ALS10A_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND</field></x3><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND</field></x1><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND</field></x5><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND</field></x2><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND</field></x6></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ALS10A/CMOS_NAND-cache.lib b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND-cache.lib
new file mode 100644
index 000000000..ab0a77bd2
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND-cache.lib
@@ -0,0 +1,130 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.cir b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.cir
new file mode 100644
index 000000000..b2846cd42
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.cir
@@ -0,0 +1,16 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND\CMOS_NAND.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/23/20 20:21:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P		
+M4  Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P		
+M2  Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M2-Pad3_ GND eSim_MOS_N		
+M3  Net-_M2-Pad3_ Net-_M3-Pad2_ GND GND eSim_MOS_N		
+U1  Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ PORT		
+v1  Net-_M1-Pad1_ GND DC		
+
+.end
diff --git a/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.cir.out b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.cir.out
new file mode 100644
index 000000000..396c0f219
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.cir.out
@@ -0,0 +1,19 @@
+* c:\fossee\esim\library\subcircuitlibrary\cmos_nand\cmos_nand.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1
+m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ gnd CMOSN W=1u L=0.5u M=1
+m3 net-_m2-pad3_ net-_m3-pad2_ gnd gnd CMOSN W=1u L=0.5u M=1
+* u1  net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ port
+v1 net-_m1-pad1_ gnd  dc 5
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.pro b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.pro
new file mode 100644
index 000000000..f63b751e5
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.pro
@@ -0,0 +1,69 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
diff --git a/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.sch b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.sch
new file mode 100644
index 000000000..1a2921fba
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.sch
@@ -0,0 +1,254 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:CMOS_NAND-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M1
+U 1 1 5EA19849
+P 5150 2100
+F 0 "M1" H 5100 2150 50  0000 R CNN
+F 1 "eSim_MOS_P" H 5200 2250 50  0000 R CNN
+F 2 "" H 5400 2200 29  0000 C CNN
+F 3 "" H 5200 2100 60  0000 C CNN
+	1    5150 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 5EA1984A
+P 5950 2050
+F 0 "M4" H 5900 2100 50  0000 R CNN
+F 1 "eSim_MOS_P" H 6000 2200 50  0000 R CNN
+F 2 "" H 6200 2150 29  0000 C CNN
+F 3 "" H 6000 2050 60  0000 C CNN
+	1    5950 2050
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 5EA1984B
+P 5350 2800
+F 0 "M2" H 5350 2650 50  0000 R CNN
+F 1 "eSim_MOS_N" H 5450 2750 50  0000 R CNN
+F 2 "" H 5650 2500 29  0000 C CNN
+F 3 "" H 5450 2600 60  0000 C CNN
+	1    5350 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M3
+U 1 1 5EA1984C
+P 5350 3450
+F 0 "M3" H 5350 3300 50  0000 R CNN
+F 1 "eSim_MOS_N" H 5450 3400 50  0000 R CNN
+F 2 "" H 5650 3150 29  0000 C CNN
+F 3 "" H 5450 3250 60  0000 C CNN
+	1    5350 3450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5300 2300 5300 2550
+Wire Wire Line
+	5300 2550 5800 2550
+Wire Wire Line
+	5800 2550 5800 2250
+Wire Wire Line
+	5400 2250 5450 2250
+Wire Wire Line
+	5450 2250 5450 1800
+Wire Wire Line
+	5300 1800 5800 1800
+Wire Wire Line
+	5300 1800 5300 1900
+Wire Wire Line
+	5600 2200 5700 2200
+Wire Wire Line
+	5600 1650 5600 2200
+Wire Wire Line
+	5800 1800 5800 1850
+Wire Wire Line
+	5550 3200 5550 3450
+Wire Wire Line
+	5550 2550 5550 2800
+Connection ~ 5550 2550
+Wire Wire Line
+	5650 3150 5800 3150
+Wire Wire Line
+	5800 3150 5800 4100
+Wire Wire Line
+	5550 3850 5550 4100
+Wire Wire Line
+	5650 3800 5650 4200
+Connection ~ 5650 4000
+Connection ~ 5450 1800
+Connection ~ 5600 1800
+Wire Wire Line
+	7400 2250 7400 1650
+Wire Wire Line
+	7400 1650 5600 1650
+Wire Wire Line
+	7400 4200 7400 3150
+Wire Wire Line
+	5650 4200 7400 4200
+Wire Wire Line
+	4650 3650 5250 3650
+Connection ~ 5650 4200
+Wire Wire Line
+	3950 2400 4650 2400
+Wire Wire Line
+	4650 2400 4650 3000
+Wire Wire Line
+	4650 3000 5250 3000
+Wire Wire Line
+	4950 2100 5000 2100
+Connection ~ 4950 3650
+Wire Wire Line
+	6400 2050 6400 4850
+Wire Wire Line
+	6400 2050 6100 2050
+Connection ~ 6050 4200
+Connection ~ 5550 2750
+Wire Wire Line
+	4950 3000 4950 2100
+Connection ~ 4950 3000
+Wire Wire Line
+	4950 3650 4950 4850
+Wire Wire Line
+	4950 4850 6400 4850
+Wire Wire Line
+	6000 2750 5550 2750
+Connection ~ 4200 2400
+Wire Wire Line
+	4650 3350 4650 3650
+Wire Wire Line
+	6000 2750 6000 3000
+$Comp
+L PORT U1
+U 1 1 5EA19AC9
+P 3600 2150
+F 0 "U1" H 3650 2250 30  0000 C CNN
+F 1 "PORT" H 3600 2150 30  0000 C CNN
+F 2 "" H 3600 2150 60  0000 C CNN
+F 3 "" H 3600 2150 60  0000 C CNN
+	1    3600 2150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5EA19B16
+P 4150 3350
+F 0 "U1" H 4200 3450 30  0000 C CNN
+F 1 "PORT" H 4150 3350 30  0000 C CNN
+F 2 "" H 4150 3350 60  0000 C CNN
+F 3 "" H 4150 3350 60  0000 C CNN
+	2    4150 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5EA19B5B
+P 6250 3000
+F 0 "U1" H 6300 3100 30  0000 C CNN
+F 1 "PORT" H 6250 3000 30  0000 C CNN
+F 2 "" H 6250 3000 60  0000 C CNN
+F 3 "" H 6250 3000 60  0000 C CNN
+	3    6250 3000
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4400 3350 4650 3350
+Wire Wire Line
+	3850 2150 3950 2150
+Wire Wire Line
+	3950 2150 3950 2400
+Text Notes 7800 2100 0    60   ~ 0
+vcc
+Text Notes 7850 3300 0    60   ~ 0
+gnd
+Text Notes 3250 2150 0    60   ~ 0
+in1\n
+Text Notes 3800 3400 0    60   ~ 0
+in2
+Text Notes 6150 2850 0    60   ~ 0
+out\n
+Wire Wire Line
+	5550 4100 5800 4100
+Connection ~ 5650 4100
+$Comp
+L DC v1
+U 1 1 5EA1AB6C
+P 7550 2700
+F 0 "v1" H 7350 2800 60  0000 C CNN
+F 1 "DC" H 7350 2650 60  0000 C CNN
+F 2 "R1" H 7250 2700 60  0000 C CNN
+F 3 "" H 7550 2700 60  0000 C CNN
+	1    7550 2700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7550 2250 7400 2250
+Wire Wire Line
+	7400 3150 7550 3150
+$Comp
+L GND #PWR1
+U 1 1 5EA1AC79
+P 6750 4300
+F 0 "#PWR1" H 6750 4050 50  0001 C CNN
+F 1 "GND" H 6750 4150 50  0000 C CNN
+F 2 "" H 6750 4300 50  0001 C CNN
+F 3 "" H 6750 4300 50  0001 C CNN
+	1    6750 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6750 4300 6750 4200
+Connection ~ 6750 4200
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.sub b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.sub
new file mode 100644
index 000000000..d40094a16
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND.sub
@@ -0,0 +1,13 @@
+* Subcircuit CMOS_NAND
+.subckt CMOS_NAND net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ 
+* c:\fossee\esim\library\subcircuitlibrary\cmos_nand\cmos_nand.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1
+m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ gnd CMOSN W=1u L=0.5u M=1
+m3 net-_m2-pad3_ net-_m3-pad2_ gnd gnd CMOSN W=1u L=0.5u M=1
+v1 net-_m1-pad1_ gnd  dc 5
+* Control Statements
+
+.ends CMOS_NAND
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ALS10A/CMOS_NAND_Previous_Values.xml b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND_Previous_Values.xml
new file mode 100644
index 000000000..e3478d8cd
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/CMOS_NAND_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1></source><model /><devicemodel><m2><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field>1u</field><field>0.5u</field><field /></m2><m4><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field>2.5u</field><field>0.5u</field><field /></m4><m3><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field>1u</field><field>0.5u</field><field /></m3><m1><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field>2.5u</field><field>0.5u</field><field /></m1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ALS10A/NMOS-180nm.lib b/library/SubcircuitLibrary/74ALS10A/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/74ALS10A/PMOS-180nm.lib b/library/SubcircuitLibrary/74ALS10A/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/74ALS10A/analysis b/library/SubcircuitLibrary/74ALS10A/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74ALS10A/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LVC1G17/74LVC1G17-cache.lib b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17-cache.lib
new file mode 100644
index 000000000..6c512720e
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.cir b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.cir
new file mode 100644
index 000000000..6898a7321
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.cir
@@ -0,0 +1,23 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74LVC1G17\74LVC1G17.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/16/26 00:21:49
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M4  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad1_ VDD eSim_MOS_P		
+M3  Net-_M3-Pad1_ Net-_M1-Pad2_ VDD VDD eSim_MOS_P		
+M5  GND Net-_M1-Pad1_ Net-_M3-Pad1_ VDD eSim_MOS_P		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND eSim_MOS_N		
+M2  Net-_M1-Pad3_ Net-_M1-Pad2_ GND GND eSim_MOS_N		
+M6  VDD Net-_M1-Pad1_ Net-_M1-Pad3_ GND eSim_MOS_N		
+M10  Net-_M10-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad3_ VDD eSim_MOS_P		
+M9  Net-_M10-Pad3_ Net-_M1-Pad1_ VDD VDD eSim_MOS_P		
+M11  GND Net-_M10-Pad1_ Net-_M10-Pad3_ VDD eSim_MOS_P		
+M7  Net-_M10-Pad1_ Net-_M1-Pad1_ Net-_M12-Pad3_ GND eSim_MOS_N		
+M8  Net-_M12-Pad3_ Net-_M1-Pad1_ GND GND eSim_MOS_N		
+M12  VDD Net-_M10-Pad1_ Net-_M12-Pad3_ GND eSim_MOS_N		
+U1  Net-_M1-Pad2_ GND VDD Net-_M10-Pad1_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.cir.out b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.cir.out
new file mode 100644
index 000000000..7bed51a63
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.cir.out
@@ -0,0 +1,26 @@
+* c:\fossee\esim\library\subcircuitlibrary\74lvc1g17\74lvc1g17.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m4 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m5 gnd net-_m1-pad1_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m6 vdd net-_m1-pad1_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m1-pad1_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m9 net-_m10-pad3_ net-_m1-pad1_ vdd vdd CMOSP W=100u L=100u M=1
+m11 gnd net-_m10-pad1_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m7 net-_m10-pad1_ net-_m1-pad1_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m12-pad3_ net-_m1-pad1_ gnd gnd CMOSN W=100u L=100u M=1
+m12 vdd net-_m10-pad1_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+* u1  net-_m1-pad2_ gnd vdd net-_m10-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.pro b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.sch b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.sch
new file mode 100644
index 000000000..7bcc6b565
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.sch
@@ -0,0 +1,356 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74LVC1G17_ckt-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M4
+U 1 1 696936A6
+P 3900 3150
+F 0 "M4" H 3850 3200 50  0000 R CNN
+F 1 "eSim_MOS_P" H 3950 3300 50  0000 R CNN
+F 2 "" H 4150 3250 29  0000 C CNN
+F 3 "" H 3950 3150 60  0000 C CNN
+	1    3900 3150
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_MOS_P M3
+U 1 1 696936A7
+P 3900 2550
+F 0 "M3" H 3850 2600 50  0000 R CNN
+F 1 "eSim_MOS_P" H 3950 2700 50  0000 R CNN
+F 2 "" H 4150 2650 29  0000 C CNN
+F 3 "" H 3950 2550 60  0000 C CNN
+	1    3900 2550
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+$EndComp
+$Comp
+L eSim_MOS_P M5
+U 1 1 696936A8
+P 4650 3000
+F 0 "M5" H 4600 3050 50  0000 R CNN
+F 1 "eSim_MOS_P" H 4700 3150 50  0000 R CNN
+F 2 "" H 4900 3100 29  0000 C CNN
+F 3 "" H 4700 3000 60  0000 C CNN
+	1    4650 3000
+	0    1    -1   0   
+$EndComp
+$Comp
+L eSim_MOS_N M1
+U 1 1 696936A9
+P 3850 3650
+F 0 "M1" H 3850 3500 50  0000 R CNN
+F 1 "eSim_MOS_N" H 3950 3600 50  0000 R CNN
+F 2 "" H 4150 3350 29  0000 C CNN
+F 3 "" H 3950 3450 60  0000 C CNN
+	1    3850 3650
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+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 696936AA
+P 3850 4250
+F 0 "M2" H 3850 4100 50  0000 R CNN
+F 1 "eSim_MOS_N" H 3950 4200 50  0000 R CNN
+F 2 "" H 4150 3950 29  0000 C CNN
+F 3 "" H 3950 4050 60  0000 C CNN
+	1    3850 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M6
+U 1 1 696936AB
+P 4850 3950
+F 0 "M6" H 4850 3800 50  0000 R CNN
+F 1 "eSim_MOS_N" H 4950 3900 50  0000 R CNN
+F 2 "" H 5150 3650 29  0000 C CNN
+F 3 "" H 4950 3750 60  0000 C CNN
+	1    4850 3950
+	0    1    1    0   
+$EndComp
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+Text GLabel 4850 4150 2    60   Input ~ 0
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+Wire Wire Line
+	3100 3400 3750 3400
+Connection ~ 3750 3400
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+Connection ~ 4650 3400
+Text GLabel 4200 2400 2    60   Input ~ 0
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+Connection ~ 3200 3400
+$Comp
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+U 1 1 696936B3
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+F 1 "eSim_MOS_P" H 6350 3300 50  0000 R CNN
+F 2 "" H 6550 3250 29  0000 C CNN
+F 3 "" H 6350 3150 60  0000 C CNN
+	1    6300 3150
+	1    0    0    1   
+$EndComp
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+F 2 "" H 6550 2650 29  0000 C CNN
+F 3 "" H 6350 2550 60  0000 C CNN
+	1    6300 2550
+	1    0    0    1   
+$EndComp
+$Comp
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+F 0 "M11" H 7000 3050 50  0000 R CNN
+F 1 "eSim_MOS_P" H 7100 3150 50  0000 R CNN
+F 2 "" H 7300 3100 29  0000 C CNN
+F 3 "" H 7100 3000 60  0000 C CNN
+	1    7050 3000
+	0    1    -1   0   
+$EndComp
+$Comp
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+F 2 "" H 6550 3350 29  0000 C CNN
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+	1    6250 3650
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+$EndComp
+$Comp
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+F 2 "" H 6550 3950 29  0000 C CNN
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+	1    6250 4250
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+$EndComp
+$Comp
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+F 2 "" H 7550 3650 29  0000 C CNN
+F 3 "" H 7350 3750 60  0000 C CNN
+	1    7250 3950
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+$EndComp
+Wire Wire Line
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+Connection ~ 6150 3400
+Wire Wire Line
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+$Comp
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+U 1 1 69693C07
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+	1    2850 3400
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+$Comp
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+U 4 1 69693C80
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+$EndComp
+$Comp
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+U 3 1 69693CB3
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+F 3 "" H 6200 2350 60  0000 C CNN
+	3    6200 2350
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+$EndComp
+Text GLabel 7350 2850 0    60   Input ~ 0
+GND
+Text GLabel 4050 4650 0    60   Input ~ 0
+GND
+Text GLabel 6450 4650 0    60   Input ~ 0
+GND
+Text GLabel 4950 2850 0    60   Input ~ 0
+GND
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.sub b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.sub
new file mode 100644
index 000000000..ddee4bd22
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17.sub
@@ -0,0 +1,20 @@
+* Subcircuit 74LVC1G17
+.subckt 74LVC1G17 net-_m1-pad2_ gnd vdd net-_m10-pad1_ 
+* c:\fossee\esim\library\subcircuitlibrary\74lvc1g17\74lvc1g17.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m4 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m5 gnd net-_m1-pad1_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m6 vdd net-_m1-pad1_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m1-pad1_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m9 net-_m10-pad3_ net-_m1-pad1_ vdd vdd CMOSP W=100u L=100u M=1
+m11 gnd net-_m10-pad1_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m7 net-_m10-pad1_ net-_m1-pad1_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m12-pad3_ net-_m1-pad1_ gnd gnd CMOSN W=100u L=100u M=1
+m12 vdd net-_m10-pad1_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+* Control Statements
+
+.ends 74LVC1G17
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LVC1G17/74LVC1G17_Previous_Values.xml b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17_Previous_Values.xml
new file mode 100644
index 000000000..6dce4cf13
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/74LVC1G17_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model /><devicemodel><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m5><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m10><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m9><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m11><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m7><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m8><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m12></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LVC1G17/NMOS-180nm.lib b/library/SubcircuitLibrary/74LVC1G17/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/74LVC1G17/PMOS-180nm.lib b/library/SubcircuitLibrary/74LVC1G17/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/74LVC1G17/analysis b/library/SubcircuitLibrary/74LVC1G17/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC1G17/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LVC2G00/74LVC2G00-cache.lib b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00-cache.lib
new file mode 100644
index 000000000..ca4c4883d
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00-cache.lib
@@ -0,0 +1,62 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_NAND
+#
+DEF CMOS_NAND X 0 40 Y Y 1 F N
+F0 "X" -100 -150 60 H V C CNN
+F1 "CMOS_NAND" 0 -50 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -350 300 300 300 N
+P 3 0 1 0 -350 300 -350 -400 300 -400 N
+X in1 1 -550 250 200 R 50 50 1 1 I
+X in2 2 -550 -300 200 R 50 50 1 1 I
+X out 3 800 0 279 L 79 79 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.cir b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.cir
new file mode 100644
index 000000000..8b220ee12
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.cir
@@ -0,0 +1,13 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74LVC2G00\74LVC2G00.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/16/26 01:20:20
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ CMOS_NAND		
+X2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ CMOS_NAND		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.cir.out b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.cir.out
new file mode 100644
index 000000000..f4aac0179
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.cir.out
@@ -0,0 +1,15 @@
+* c:\fossee\esim\library\subcircuitlibrary\74lvc2g00\74lvc2g00.cir
+
+.include CMOS_NAND.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ CMOS_NAND
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ CMOS_NAND
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.pro b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.sch b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.sch
new file mode 100644
index 000000000..2f747a495
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.sch
@@ -0,0 +1,145 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74LVC2G00_ckt-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CMOS_NAND X1
+U 1 1 696944E2
+P 6400 4100
+F 0 "X1" H 6300 3950 60  0000 C CNN
+F 1 "CMOS_NAND" H 6400 4050 60  0000 C CNN
+F 2 "" H 6400 4100 60  0001 C CNN
+F 3 "" H 6400 4100 60  0001 C CNN
+	1    6400 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L CMOS_NAND X2
+U 1 1 696944E3
+P 8300 4050
+F 0 "X2" H 8200 3900 60  0000 C CNN
+F 1 "CMOS_NAND" H 8300 4000 60  0000 C CNN
+F 2 "" H 8300 4050 60  0001 C CNN
+F 3 "" H 8300 4050 60  0001 C CNN
+	1    8300 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 69694B2A
+P 5600 3850
+F 0 "U1" H 5650 3950 30  0000 C CNN
+F 1 "PORT" H 5600 3850 30  0000 C CNN
+F 2 "" H 5600 3850 60  0000 C CNN
+F 3 "" H 5600 3850 60  0000 C CNN
+	1    5600 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 69694B55
+P 5600 4400
+F 0 "U1" H 5650 4500 30  0000 C CNN
+F 1 "PORT" H 5600 4400 30  0000 C CNN
+F 2 "" H 5600 4400 60  0000 C CNN
+F 3 "" H 5600 4400 60  0000 C CNN
+	2    5600 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 69694B72
+P 9350 4050
+F 0 "U1" H 9400 4150 30  0000 C CNN
+F 1 "PORT" H 9350 4050 30  0000 C CNN
+F 2 "" H 9350 4050 60  0000 C CNN
+F 3 "" H 9350 4050 60  0000 C CNN
+	6    9350 4050
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 69694B93
+P 7500 3800
+F 0 "U1" H 7550 3900 30  0000 C CNN
+F 1 "PORT" H 7500 3800 30  0000 C CNN
+F 2 "" H 7500 3800 60  0000 C CNN
+F 3 "" H 7500 3800 60  0000 C CNN
+	4    7500 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 69694BB6
+P 7500 4350
+F 0 "U1" H 7550 4450 30  0000 C CNN
+F 1 "PORT" H 7500 4350 30  0000 C CNN
+F 2 "" H 7500 4350 60  0000 C CNN
+F 3 "" H 7500 4350 60  0000 C CNN
+	5    7500 4350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 69694BDD
+P 7450 4100
+F 0 "U1" H 7500 4200 30  0000 C CNN
+F 1 "PORT" H 7450 4100 30  0000 C CNN
+F 2 "" H 7450 4100 60  0000 C CNN
+F 3 "" H 7450 4100 60  0000 C CNN
+	3    7450 4100
+	-1   0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.sub b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.sub
new file mode 100644
index 000000000..ad9427fdc
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00.sub
@@ -0,0 +1,9 @@
+* Subcircuit 74LVC2G00
+.subckt 74LVC2G00 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\fossee\esim\library\subcircuitlibrary\74lvc2g00\74lvc2g00.cir
+.include CMOS_NAND.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ CMOS_NAND
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ CMOS_NAND
+* Control Statements
+
+.ends 74LVC2G00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LVC2G00/74LVC2G00_Previous_Values.xml b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00_Previous_Values.xml
new file mode 100644
index 000000000..022147672
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/74LVC2G00_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND</field></x2></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND-cache.lib b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND-cache.lib
new file mode 100644
index 000000000..ab0a77bd2
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND-cache.lib
@@ -0,0 +1,130 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.cir b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.cir
new file mode 100644
index 000000000..b2846cd42
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.cir
@@ -0,0 +1,16 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND\CMOS_NAND.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/23/20 20:21:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P		
+M4  Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P		
+M2  Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M2-Pad3_ GND eSim_MOS_N		
+M3  Net-_M2-Pad3_ Net-_M3-Pad2_ GND GND eSim_MOS_N		
+U1  Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ PORT		
+v1  Net-_M1-Pad1_ GND DC		
+
+.end
diff --git a/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.cir.out b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.cir.out
new file mode 100644
index 000000000..396c0f219
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.cir.out
@@ -0,0 +1,19 @@
+* c:\fossee\esim\library\subcircuitlibrary\cmos_nand\cmos_nand.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1
+m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ gnd CMOSN W=1u L=0.5u M=1
+m3 net-_m2-pad3_ net-_m3-pad2_ gnd gnd CMOSN W=1u L=0.5u M=1
+* u1  net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ port
+v1 net-_m1-pad1_ gnd  dc 5
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.pro b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.pro
new file mode 100644
index 000000000..f63b751e5
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.pro
@@ -0,0 +1,69 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
diff --git a/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.sch b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.sch
new file mode 100644
index 000000000..1a2921fba
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.sch
@@ -0,0 +1,254 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:CMOS_NAND-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M1
+U 1 1 5EA19849
+P 5150 2100
+F 0 "M1" H 5100 2150 50  0000 R CNN
+F 1 "eSim_MOS_P" H 5200 2250 50  0000 R CNN
+F 2 "" H 5400 2200 29  0000 C CNN
+F 3 "" H 5200 2100 60  0000 C CNN
+	1    5150 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 5EA1984A
+P 5950 2050
+F 0 "M4" H 5900 2100 50  0000 R CNN
+F 1 "eSim_MOS_P" H 6000 2200 50  0000 R CNN
+F 2 "" H 6200 2150 29  0000 C CNN
+F 3 "" H 6000 2050 60  0000 C CNN
+	1    5950 2050
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 5EA1984B
+P 5350 2800
+F 0 "M2" H 5350 2650 50  0000 R CNN
+F 1 "eSim_MOS_N" H 5450 2750 50  0000 R CNN
+F 2 "" H 5650 2500 29  0000 C CNN
+F 3 "" H 5450 2600 60  0000 C CNN
+	1    5350 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M3
+U 1 1 5EA1984C
+P 5350 3450
+F 0 "M3" H 5350 3300 50  0000 R CNN
+F 1 "eSim_MOS_N" H 5450 3400 50  0000 R CNN
+F 2 "" H 5650 3150 29  0000 C CNN
+F 3 "" H 5450 3250 60  0000 C CNN
+	1    5350 3450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5300 2300 5300 2550
+Wire Wire Line
+	5300 2550 5800 2550
+Wire Wire Line
+	5800 2550 5800 2250
+Wire Wire Line
+	5400 2250 5450 2250
+Wire Wire Line
+	5450 2250 5450 1800
+Wire Wire Line
+	5300 1800 5800 1800
+Wire Wire Line
+	5300 1800 5300 1900
+Wire Wire Line
+	5600 2200 5700 2200
+Wire Wire Line
+	5600 1650 5600 2200
+Wire Wire Line
+	5800 1800 5800 1850
+Wire Wire Line
+	5550 3200 5550 3450
+Wire Wire Line
+	5550 2550 5550 2800
+Connection ~ 5550 2550
+Wire Wire Line
+	5650 3150 5800 3150
+Wire Wire Line
+	5800 3150 5800 4100
+Wire Wire Line
+	5550 3850 5550 4100
+Wire Wire Line
+	5650 3800 5650 4200
+Connection ~ 5650 4000
+Connection ~ 5450 1800
+Connection ~ 5600 1800
+Wire Wire Line
+	7400 2250 7400 1650
+Wire Wire Line
+	7400 1650 5600 1650
+Wire Wire Line
+	7400 4200 7400 3150
+Wire Wire Line
+	5650 4200 7400 4200
+Wire Wire Line
+	4650 3650 5250 3650
+Connection ~ 5650 4200
+Wire Wire Line
+	3950 2400 4650 2400
+Wire Wire Line
+	4650 2400 4650 3000
+Wire Wire Line
+	4650 3000 5250 3000
+Wire Wire Line
+	4950 2100 5000 2100
+Connection ~ 4950 3650
+Wire Wire Line
+	6400 2050 6400 4850
+Wire Wire Line
+	6400 2050 6100 2050
+Connection ~ 6050 4200
+Connection ~ 5550 2750
+Wire Wire Line
+	4950 3000 4950 2100
+Connection ~ 4950 3000
+Wire Wire Line
+	4950 3650 4950 4850
+Wire Wire Line
+	4950 4850 6400 4850
+Wire Wire Line
+	6000 2750 5550 2750
+Connection ~ 4200 2400
+Wire Wire Line
+	4650 3350 4650 3650
+Wire Wire Line
+	6000 2750 6000 3000
+$Comp
+L PORT U1
+U 1 1 5EA19AC9
+P 3600 2150
+F 0 "U1" H 3650 2250 30  0000 C CNN
+F 1 "PORT" H 3600 2150 30  0000 C CNN
+F 2 "" H 3600 2150 60  0000 C CNN
+F 3 "" H 3600 2150 60  0000 C CNN
+	1    3600 2150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5EA19B16
+P 4150 3350
+F 0 "U1" H 4200 3450 30  0000 C CNN
+F 1 "PORT" H 4150 3350 30  0000 C CNN
+F 2 "" H 4150 3350 60  0000 C CNN
+F 3 "" H 4150 3350 60  0000 C CNN
+	2    4150 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5EA19B5B
+P 6250 3000
+F 0 "U1" H 6300 3100 30  0000 C CNN
+F 1 "PORT" H 6250 3000 30  0000 C CNN
+F 2 "" H 6250 3000 60  0000 C CNN
+F 3 "" H 6250 3000 60  0000 C CNN
+	3    6250 3000
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4400 3350 4650 3350
+Wire Wire Line
+	3850 2150 3950 2150
+Wire Wire Line
+	3950 2150 3950 2400
+Text Notes 7800 2100 0    60   ~ 0
+vcc
+Text Notes 7850 3300 0    60   ~ 0
+gnd
+Text Notes 3250 2150 0    60   ~ 0
+in1\n
+Text Notes 3800 3400 0    60   ~ 0
+in2
+Text Notes 6150 2850 0    60   ~ 0
+out\n
+Wire Wire Line
+	5550 4100 5800 4100
+Connection ~ 5650 4100
+$Comp
+L DC v1
+U 1 1 5EA1AB6C
+P 7550 2700
+F 0 "v1" H 7350 2800 60  0000 C CNN
+F 1 "DC" H 7350 2650 60  0000 C CNN
+F 2 "R1" H 7250 2700 60  0000 C CNN
+F 3 "" H 7550 2700 60  0000 C CNN
+	1    7550 2700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7550 2250 7400 2250
+Wire Wire Line
+	7400 3150 7550 3150
+$Comp
+L GND #PWR1
+U 1 1 5EA1AC79
+P 6750 4300
+F 0 "#PWR1" H 6750 4050 50  0001 C CNN
+F 1 "GND" H 6750 4150 50  0000 C CNN
+F 2 "" H 6750 4300 50  0001 C CNN
+F 3 "" H 6750 4300 50  0001 C CNN
+	1    6750 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6750 4300 6750 4200
+Connection ~ 6750 4200
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.sub b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.sub
new file mode 100644
index 000000000..d40094a16
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND.sub
@@ -0,0 +1,13 @@
+* Subcircuit CMOS_NAND
+.subckt CMOS_NAND net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ 
+* c:\fossee\esim\library\subcircuitlibrary\cmos_nand\cmos_nand.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1
+m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ gnd CMOSN W=1u L=0.5u M=1
+m3 net-_m2-pad3_ net-_m3-pad2_ gnd gnd CMOSN W=1u L=0.5u M=1
+v1 net-_m1-pad1_ gnd  dc 5
+* Control Statements
+
+.ends CMOS_NAND
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND_Previous_Values.xml b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND_Previous_Values.xml
new file mode 100644
index 000000000..e3478d8cd
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/CMOS_NAND_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1></source><model /><devicemodel><m2><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field>1u</field><field>0.5u</field><field /></m2><m4><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field>2.5u</field><field>0.5u</field><field /></m4><m3><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field>1u</field><field>0.5u</field><field /></m3><m1><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field>2.5u</field><field>0.5u</field><field /></m1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LVC2G00/NMOS-180nm.lib b/library/SubcircuitLibrary/74LVC2G00/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/74LVC2G00/PMOS-180nm.lib b/library/SubcircuitLibrary/74LVC2G00/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/74LVC2G00/analysis b/library/SubcircuitLibrary/74LVC2G00/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74LVC2G00/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD40106B/CD40106B-cache.lib b/library/SubcircuitLibrary/CD40106B/CD40106B-cache.lib
new file mode 100644
index 000000000..6c512720e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/CD40106B-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD40106B/CD40106B.cir b/library/SubcircuitLibrary/CD40106B/CD40106B.cir
new file mode 100644
index 000000000..bd1068638
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/CD40106B.cir
@@ -0,0 +1,47 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD40106B\CD40106B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/16/26 00:52:38
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M4  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad1_ VDD eSim_MOS_P		
+M3  Net-_M3-Pad1_ Net-_M1-Pad2_ VDD VDD eSim_MOS_P		
+M5  GND Net-_M1-Pad1_ Net-_M3-Pad1_ VDD eSim_MOS_P		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND eSim_MOS_N		
+M2  Net-_M1-Pad3_ Net-_M1-Pad2_ GND GND eSim_MOS_N		
+M6  VDD Net-_M1-Pad1_ Net-_M1-Pad3_ GND eSim_MOS_N		
+M16  Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M15-Pad1_ VDD eSim_MOS_P		
+M15  Net-_M15-Pad1_ Net-_M13-Pad2_ VDD VDD eSim_MOS_P		
+M21  GND Net-_M13-Pad1_ Net-_M15-Pad1_ VDD eSim_MOS_P		
+M13  Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M13-Pad3_ GND eSim_MOS_N		
+M14  Net-_M13-Pad3_ Net-_M13-Pad2_ GND GND eSim_MOS_N		
+M22  VDD Net-_M13-Pad1_ Net-_M13-Pad3_ GND eSim_MOS_N		
+M28  Net-_M25-Pad1_ Net-_M25-Pad2_ Net-_M27-Pad1_ VDD eSim_MOS_P		
+M27  Net-_M27-Pad1_ Net-_M25-Pad2_ VDD VDD eSim_MOS_P		
+M29  GND Net-_M25-Pad1_ Net-_M27-Pad1_ VDD eSim_MOS_P		
+M25  Net-_M25-Pad1_ Net-_M25-Pad2_ Net-_M25-Pad3_ GND eSim_MOS_N		
+M26  Net-_M25-Pad3_ Net-_M25-Pad2_ GND GND eSim_MOS_N		
+M30  VDD Net-_M25-Pad1_ Net-_M25-Pad3_ GND eSim_MOS_N		
+M34  Net-_M31-Pad1_ Net-_M31-Pad2_ Net-_M33-Pad1_ VDD eSim_MOS_P		
+M33  Net-_M33-Pad1_ Net-_M31-Pad2_ VDD VDD eSim_MOS_P		
+M35  GND Net-_M31-Pad1_ Net-_M33-Pad1_ VDD eSim_MOS_P		
+M31  Net-_M31-Pad1_ Net-_M31-Pad2_ Net-_M31-Pad3_ GND eSim_MOS_N		
+M32  Net-_M31-Pad3_ Net-_M31-Pad2_ GND GND eSim_MOS_N		
+M36  VDD Net-_M31-Pad1_ Net-_M31-Pad3_ GND eSim_MOS_N		
+M10  Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ VDD eSim_MOS_P		
+M9  Net-_M10-Pad3_ Net-_M10-Pad2_ VDD VDD eSim_MOS_P		
+M11  GND Net-_M10-Pad1_ Net-_M10-Pad3_ VDD eSim_MOS_P		
+M7  Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M12-Pad3_ GND eSim_MOS_N		
+M8  Net-_M12-Pad3_ Net-_M10-Pad2_ GND GND eSim_MOS_N		
+M12  VDD Net-_M10-Pad1_ Net-_M12-Pad3_ GND eSim_MOS_N		
+M20  Net-_M17-Pad1_ Net-_M17-Pad2_ Net-_M19-Pad1_ VDD eSim_MOS_P		
+M19  Net-_M19-Pad1_ Net-_M17-Pad2_ VDD VDD eSim_MOS_P		
+M23  GND Net-_M17-Pad1_ Net-_M19-Pad1_ VDD eSim_MOS_P		
+M17  Net-_M17-Pad1_ Net-_M17-Pad2_ Net-_M17-Pad3_ GND eSim_MOS_N		
+M18  Net-_M17-Pad3_ Net-_M17-Pad2_ GND GND eSim_MOS_N		
+M24  VDD Net-_M17-Pad1_ Net-_M17-Pad3_ GND eSim_MOS_N		
+U1  Net-_M1-Pad2_ Net-_M10-Pad2_ GND Net-_M1-Pad1_ Net-_M13-Pad2_ Net-_M17-Pad2_ Net-_M10-Pad1_ Net-_M13-Pad1_ Net-_M25-Pad2_ Net-_M17-Pad1_ VDD Net-_M31-Pad2_ Net-_M25-Pad1_ Net-_M31-Pad1_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/CD40106B/CD40106B.cir.out b/library/SubcircuitLibrary/CD40106B/CD40106B.cir.out
new file mode 100644
index 000000000..b0a9c1447
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/CD40106B.cir.out
@@ -0,0 +1,50 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd40106b\cd40106b.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m4 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m5 gnd net-_m1-pad1_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m6 vdd net-_m1-pad1_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m16 net-_m13-pad1_ net-_m13-pad2_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m15 net-_m15-pad1_ net-_m13-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m21 gnd net-_m13-pad1_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m14 net-_m13-pad3_ net-_m13-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m22 vdd net-_m13-pad1_ net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m28 net-_m25-pad1_ net-_m25-pad2_ net-_m27-pad1_ vdd CMOSP W=100u L=100u M=1
+m27 net-_m27-pad1_ net-_m25-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m29 gnd net-_m25-pad1_ net-_m27-pad1_ vdd CMOSP W=100u L=100u M=1
+m25 net-_m25-pad1_ net-_m25-pad2_ net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m26 net-_m25-pad3_ net-_m25-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m30 vdd net-_m25-pad1_ net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m34 net-_m31-pad1_ net-_m31-pad2_ net-_m33-pad1_ vdd CMOSP W=100u L=100u M=1
+m33 net-_m33-pad1_ net-_m31-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m35 gnd net-_m31-pad1_ net-_m33-pad1_ vdd CMOSP W=100u L=100u M=1
+m31 net-_m31-pad1_ net-_m31-pad2_ net-_m31-pad3_ gnd CMOSN W=100u L=100u M=1
+m32 net-_m31-pad3_ net-_m31-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m36 vdd net-_m31-pad1_ net-_m31-pad3_ gnd CMOSN W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m9 net-_m10-pad3_ net-_m10-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m11 gnd net-_m10-pad1_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m7 net-_m10-pad1_ net-_m10-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m12-pad3_ net-_m10-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m12 vdd net-_m10-pad1_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m20 net-_m17-pad1_ net-_m17-pad2_ net-_m19-pad1_ vdd CMOSP W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m17-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m23 gnd net-_m17-pad1_ net-_m19-pad1_ vdd CMOSP W=100u L=100u M=1
+m17 net-_m17-pad1_ net-_m17-pad2_ net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+m18 net-_m17-pad3_ net-_m17-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m24 vdd net-_m17-pad1_ net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+* u1  net-_m1-pad2_ net-_m10-pad2_ gnd net-_m1-pad1_ net-_m13-pad2_ net-_m17-pad2_ net-_m10-pad1_ net-_m13-pad1_ net-_m25-pad2_ net-_m17-pad1_ vdd net-_m31-pad2_ net-_m25-pad1_ net-_m31-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD40106B/CD40106B.pro b/library/SubcircuitLibrary/CD40106B/CD40106B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/CD40106B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
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+LibName4=microcontrollers
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+LibName7=analog_switches
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+LibName27=74xx
+LibName28=cmos4000
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+LibName37=eSim_Nghdl
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diff --git a/library/SubcircuitLibrary/CD40106B/CD40106B.sch b/library/SubcircuitLibrary/CD40106B/CD40106B.sch
new file mode 100644
index 000000000..4ea7c75be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/CD40106B.sch
@@ -0,0 +1,988 @@
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+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SchmittTrigger_invert-cache
+EELAYER 25 0
+EELAYER END
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+encoding utf-8
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+$EndComp
+$Comp
+L eSim_MOS_N M17
+U 1 1 69693DD9
+P 5150 6550
+F 0 "M17" H 5150 6400 50  0000 R CNN
+F 1 "eSim_MOS_N" H 5250 6500 50  0000 R CNN
+F 2 "" H 5450 6250 29  0000 C CNN
+F 3 "" H 5250 6350 60  0000 C CNN
+	1    5150 6550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M18
+U 1 1 69693DDA
+P 5150 7150
+F 0 "M18" H 5150 7000 50  0000 R CNN
+F 1 "eSim_MOS_N" H 5250 7100 50  0000 R CNN
+F 2 "" H 5450 6850 29  0000 C CNN
+F 3 "" H 5250 6950 60  0000 C CNN
+	1    5150 7150
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M24
+U 1 1 69693DDB
+P 6150 6850
+F 0 "M24" H 6150 6700 50  0000 R CNN
+F 1 "eSim_MOS_N" H 6250 6800 50  0000 R CNN
+F 2 "" H 6450 6550 29  0000 C CNN
+F 3 "" H 6250 6650 60  0000 C CNN
+	1    6150 6850
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	5050 5450 5050 7350
+Connection ~ 5050 6050
+Connection ~ 5050 6750
+Wire Wire Line
+	5350 5650 5350 5850
+Wire Wire Line
+	5350 6250 5350 6550
+Wire Wire Line
+	5350 6950 5350 7150
+Wire Wire Line
+	5450 5300 5450 5250
+Wire Wire Line
+	5350 5250 5500 5250
+Wire Wire Line
+	5450 5900 5500 5900
+Wire Wire Line
+	5500 5900 5500 5250
+Connection ~ 5450 5250
+Wire Wire Line
+	5450 7500 5450 7550
+Wire Wire Line
+	5350 7550 5500 7550
+Wire Wire Line
+	5450 6900 5500 6900
+Wire Wire Line
+	5500 6900 5500 7550
+Connection ~ 5450 7550
+Wire Wire Line
+	5750 5750 5350 5750
+Connection ~ 5350 5750
+Wire Wire Line
+	5750 7050 5350 7050
+Connection ~ 5350 7050
+Wire Wire Line
+	5800 5650 5500 5650
+Connection ~ 5500 5650
+Wire Wire Line
+	5800 7150 5500 7150
+Connection ~ 5500 7150
+Wire Wire Line
+	5350 6400 5950 6400
+Wire Wire Line
+	5950 6050 5950 6750
+Connection ~ 5350 6400
+Connection ~ 5950 6400
+Wire Wire Line
+	6150 5750 6250 5750
+Text GLabel 6150 7050 2    60   Input ~ 0
+VDD
+Wire Wire Line
+	4400 6300 5050 6300
+Connection ~ 5050 6300
+Connection ~ 5950 6300
+Text GLabel 5500 5300 2    60   Input ~ 0
+VDD
+Connection ~ 4500 6300
+Wire Wire Line
+	5950 6300 6300 6300
+Text GLabel 2800 2200 0    60   Input ~ 0
+GND
+$Comp
+L PORT U1
+U 1 1 69694417
+P 700 2750
+F 0 "U1" H 750 2850 30  0000 C CNN
+F 1 "PORT" H 700 2750 30  0000 C CNN
+F 2 "" H 700 2750 60  0000 C CNN
+F 3 "" H 700 2750 60  0000 C CNN
+	1    700  2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 696944AC
+P 3100 2750
+F 0 "U1" H 3150 2850 30  0000 C CNN
+F 1 "PORT" H 3100 2750 30  0000 C CNN
+F 2 "" H 3100 2750 60  0000 C CNN
+F 3 "" H 3100 2750 60  0000 C CNN
+	4    3100 2750
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 69696E47
+P 3650 2850
+F 0 "U1" H 3700 2950 30  0000 C CNN
+F 1 "PORT" H 3650 2850 30  0000 C CNN
+F 2 "" H 3650 2850 60  0000 C CNN
+F 3 "" H 3650 2850 60  0000 C CNN
+	5    3650 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 69696F59
+P 6050 2850
+F 0 "U1" H 6100 2950 30  0000 C CNN
+F 1 "PORT" H 6050 2850 30  0000 C CNN
+F 2 "" H 6050 2850 60  0000 C CNN
+F 3 "" H 6050 2850 60  0000 C CNN
+	8    6050 2850
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 69699102
+P 6200 1800
+F 0 "U1" H 6250 1900 30  0000 C CNN
+F 1 "PORT" H 6200 1800 30  0000 C CNN
+F 2 "" H 6200 1800 60  0000 C CNN
+F 3 "" H 6200 1800 60  0000 C CNN
+	9    6200 1800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6969917F
+P 8600 1800
+F 0 "U1" H 8650 1900 30  0000 C CNN
+F 1 "PORT" H 8600 1800 30  0000 C CNN
+F 2 "" H 8600 1800 60  0000 C CNN
+F 3 "" H 8600 1800 60  0000 C CNN
+	13   8600 1800
+	-1   0    0    -1  
+$EndComp
+Text GLabel 5750 2300 0    60   Input ~ 0
+GND
+Text GLabel 8300 1250 0    60   Input ~ 0
+GND
+Text GLabel 10600 2750 0    60   Input ~ 0
+GND
+$Comp
+L PORT U1
+U 12 1 6969B1ED
+P 8500 3300
+F 0 "U1" H 8550 3400 30  0000 C CNN
+F 1 "PORT" H 8500 3300 30  0000 C CNN
+F 2 "" H 8500 3300 60  0000 C CNN
+F 3 "" H 8500 3300 60  0000 C CNN
+	12   8500 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6969B29E
+P 10900 3300
+F 0 "U1" H 10950 3400 30  0000 C CNN
+F 1 "PORT" H 10900 3300 30  0000 C CNN
+F 2 "" H 10900 3300 60  0000 C CNN
+F 3 "" H 10900 3300 60  0000 C CNN
+	14   10900 3300
+	-1   0    0    -1  
+$EndComp
+Text GLabel 9800 4550 0    60   Input ~ 0
+GND
+Text GLabel 7500 3050 0    60   Input ~ 0
+GND
+Text GLabel 4950 4100 0    60   Input ~ 0
+GND
+Text GLabel 2750 6950 0    60   Input ~ 0
+GND
+Text GLabel 6750 4050 0    60   Input ~ 0
+VDD
+$Comp
+L PORT U1
+U 3 1 6969CE29
+P 3000 6950
+F 0 "U1" H 3050 7050 30  0000 C CNN
+F 1 "PORT" H 3000 6950 30  0000 C CNN
+F 2 "" H 3000 6950 60  0000 C CNN
+F 3 "" H 3000 6950 60  0000 C CNN
+	3    3000 6950
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6969DF92
+P 1850 4800
+F 0 "U1" H 1900 4900 30  0000 C CNN
+F 1 "PORT" H 1850 4800 30  0000 C CNN
+F 2 "" H 1850 4800 60  0000 C CNN
+F 3 "" H 1850 4800 60  0000 C CNN
+	2    1850 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6969E051
+P 4250 4800
+F 0 "U1" H 4300 4900 30  0000 C CNN
+F 1 "PORT" H 4250 4800 30  0000 C CNN
+F 2 "" H 4250 4800 60  0000 C CNN
+F 3 "" H 4250 4800 60  0000 C CNN
+	7    4250 4800
+	-1   0    0    -1  
+$EndComp
+Text GLabel 3100 6050 0    60   Input ~ 0
+GND
+Text GLabel 5450 7550 0    60   Input ~ 0
+GND
+Text GLabel 6250 5750 0    60   Input ~ 0
+GND
+Text GLabel 3950 4250 0    60   Input ~ 0
+GND
+Text GLabel 2000 4000 0    60   Input ~ 0
+GND
+$Comp
+L PORT U1
+U 10 1 6969E59B
+P 6550 6300
+F 0 "U1" H 6600 6400 30  0000 C CNN
+F 1 "PORT" H 6550 6300 30  0000 C CNN
+F 2 "" H 6550 6300 60  0000 C CNN
+F 3 "" H 6550 6300 60  0000 C CNN
+	10   6550 6300
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6969E68E
+P 4150 6300
+F 0 "U1" H 4200 6400 30  0000 C CNN
+F 1 "PORT" H 4150 6300 30  0000 C CNN
+F 2 "" H 4150 6300 60  0000 C CNN
+F 3 "" H 4150 6300 60  0000 C CNN
+	6    4150 6300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6969E83E
+P 7000 4050
+F 0 "U1" H 7050 4150 30  0000 C CNN
+F 1 "PORT" H 7000 4050 30  0000 C CNN
+F 2 "" H 7000 4050 60  0000 C CNN
+F 3 "" H 7000 4050 60  0000 C CNN
+	11   7000 4050
+	-1   0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD40106B/CD40106B.sub b/library/SubcircuitLibrary/CD40106B/CD40106B.sub
new file mode 100644
index 000000000..74c4ed49e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/CD40106B.sub
@@ -0,0 +1,44 @@
+* Subcircuit CD40106B
+.subckt CD40106B net-_m1-pad2_ net-_m10-pad2_ gnd net-_m1-pad1_ net-_m13-pad2_ net-_m17-pad2_ net-_m10-pad1_ net-_m13-pad1_ net-_m25-pad2_ net-_m17-pad1_ vdd net-_m31-pad2_ net-_m25-pad1_ net-_m31-pad1_ 
+* c:\fossee\esim\library\subcircuitlibrary\cd40106b\cd40106b.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m4 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m5 gnd net-_m1-pad1_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m6 vdd net-_m1-pad1_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m16 net-_m13-pad1_ net-_m13-pad2_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m15 net-_m15-pad1_ net-_m13-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m21 gnd net-_m13-pad1_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m14 net-_m13-pad3_ net-_m13-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m22 vdd net-_m13-pad1_ net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m28 net-_m25-pad1_ net-_m25-pad2_ net-_m27-pad1_ vdd CMOSP W=100u L=100u M=1
+m27 net-_m27-pad1_ net-_m25-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m29 gnd net-_m25-pad1_ net-_m27-pad1_ vdd CMOSP W=100u L=100u M=1
+m25 net-_m25-pad1_ net-_m25-pad2_ net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m26 net-_m25-pad3_ net-_m25-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m30 vdd net-_m25-pad1_ net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m34 net-_m31-pad1_ net-_m31-pad2_ net-_m33-pad1_ vdd CMOSP W=100u L=100u M=1
+m33 net-_m33-pad1_ net-_m31-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m35 gnd net-_m31-pad1_ net-_m33-pad1_ vdd CMOSP W=100u L=100u M=1
+m31 net-_m31-pad1_ net-_m31-pad2_ net-_m31-pad3_ gnd CMOSN W=100u L=100u M=1
+m32 net-_m31-pad3_ net-_m31-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m36 vdd net-_m31-pad1_ net-_m31-pad3_ gnd CMOSN W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m9 net-_m10-pad3_ net-_m10-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m11 gnd net-_m10-pad1_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m7 net-_m10-pad1_ net-_m10-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m12-pad3_ net-_m10-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m12 vdd net-_m10-pad1_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m20 net-_m17-pad1_ net-_m17-pad2_ net-_m19-pad1_ vdd CMOSP W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m17-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m23 gnd net-_m17-pad1_ net-_m19-pad1_ vdd CMOSP W=100u L=100u M=1
+m17 net-_m17-pad1_ net-_m17-pad2_ net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+m18 net-_m17-pad3_ net-_m17-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m24 vdd net-_m17-pad1_ net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+* Control Statements
+
+.ends CD40106B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD40106B/CD40106B_Previous_Values.xml b/library/SubcircuitLibrary/CD40106B/CD40106B_Previous_Values.xml
new file mode 100644
index 000000000..82898c83d
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/CD40106B_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model /><devicemodel><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m5><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m16><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m15><m21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m21><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m13><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m14><m22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m22><m28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m28><m27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m27><m29><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m29><m25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m25><m26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m26><m30><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m30><m34><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m34><m33><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m33><m35><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m35><m31><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m31><m32><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m32><m36><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m36><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m10><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m9><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m11><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m7><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m8><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m12><m20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m20><m19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m19><m23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m23><m17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m17><m18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m18><m24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m24></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD40106B/NMOS-180nm.lib b/library/SubcircuitLibrary/CD40106B/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/CD40106B/PMOS-180nm.lib b/library/SubcircuitLibrary/CD40106B/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/CD40106B/analysis b/library/SubcircuitLibrary/CD40106B/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD40106B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICS83840/ICS83840-cache.lib b/library/SubcircuitLibrary/ICS83840/ICS83840-cache.lib
new file mode 100644
index 000000000..2750920cd
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/ICS83840-cache.lib
@@ -0,0 +1,161 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/ICS83840/ICS83840.cir b/library/SubcircuitLibrary/ICS83840/ICS83840.cir
new file mode 100644
index 000000000..8c1522a0a
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/ICS83840.cir
@@ -0,0 +1,51 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\ICS83840\ICS83840.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/30/26 15:38:54
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U6  Net-_M6-Pad2_ Net-_U6-Pad2_ adc_bridge_1		
+U8  Net-_U6-Pad2_ Net-_U11-Pad1_ d_inverter		
+M4  HP0 Net-_M4-Pad2_ Net-_M4-Pad3_ GND eSim_MOS_N		
+M6  HP0 Net-_M6-Pad2_ Net-_M4-Pad3_ VDD eSim_MOS_P		
+M11  GND Net-_M11-Pad2_ Net-_M11-Pad3_ GND eSim_MOS_N		
+U20  Net-_U17-Pad2_ Net-_U20-Pad2_ d_inverter		
+U11  Net-_U11-Pad1_ Net-_M4-Pad2_ dac_bridge_1		
+U17  Net-_M4-Pad2_ Net-_U17-Pad2_ adc_bridge_1		
+U22  Net-_U20-Pad2_ Net-_M11-Pad2_ dac_bridge_1		
+R3  Net-_M11-Pad3_ Net-_M4-Pad3_ 20		
+U12  Net-_M9-Pad2_ Net-_U12-Pad2_ adc_bridge_1		
+U14  Net-_U12-Pad2_ Net-_U14-Pad2_ d_inverter		
+M8  HP0 Net-_M8-Pad2_ Net-_M8-Pad3_ GND eSim_MOS_N		
+M9  HP0 Net-_M9-Pad2_ Net-_M8-Pad3_ VDD eSim_MOS_P		
+M12  GND Net-_M12-Pad2_ Net-_M12-Pad3_ GND eSim_MOS_N		
+U24  Net-_U23-Pad2_ Net-_U24-Pad2_ d_inverter		
+U18  Net-_U14-Pad2_ Net-_M8-Pad2_ dac_bridge_1		
+U23  Net-_M8-Pad2_ Net-_U23-Pad2_ adc_bridge_1		
+U25  Net-_U24-Pad2_ Net-_M12-Pad2_ dac_bridge_1		
+R4  Net-_M12-Pad3_ Net-_M8-Pad3_ 20		
+U5  Net-_M5-Pad2_ Net-_U5-Pad2_ adc_bridge_1		
+U7  Net-_U5-Pad2_ Net-_U10-Pad1_ d_inverter		
+M3  HP0 Net-_M3-Pad2_ Net-_M3-Pad3_ GND eSim_MOS_N		
+M5  HP0 Net-_M5-Pad2_ Net-_M3-Pad3_ VDD eSim_MOS_P		
+M10  GND Net-_M10-Pad2_ Net-_M10-Pad3_ GND eSim_MOS_N		
+U19  Net-_U16-Pad2_ Net-_U19-Pad2_ d_inverter		
+U10  Net-_U10-Pad1_ Net-_M3-Pad2_ dac_bridge_1		
+U16  Net-_M3-Pad2_ Net-_U16-Pad2_ adc_bridge_1		
+U21  Net-_U19-Pad2_ Net-_M10-Pad2_ dac_bridge_1		
+R2  Net-_M10-Pad3_ Net-_M3-Pad3_ 20		
+U2  Net-_M2-Pad2_ Net-_U2-Pad2_ adc_bridge_1		
+U3  Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter		
+M1  HP0 Net-_M1-Pad2_ Net-_M1-Pad3_ GND eSim_MOS_N		
+M2  HP0 Net-_M2-Pad2_ Net-_M1-Pad3_ VDD eSim_MOS_P		
+M7  GND Net-_M7-Pad2_ Net-_M7-Pad3_ GND eSim_MOS_N		
+U13  Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter		
+U4  Net-_U3-Pad2_ Net-_M1-Pad2_ dac_bridge_1		
+U9  Net-_M1-Pad2_ Net-_U13-Pad1_ adc_bridge_1		
+U15  Net-_U13-Pad2_ Net-_M7-Pad2_ dac_bridge_1		
+R1  Net-_M7-Pad3_ Net-_M1-Pad3_ 20		
+U1  Net-_M2-Pad2_ HP0 Net-_M5-Pad2_ Net-_M6-Pad2_ Net-_M9-Pad2_ Net-_M1-Pad3_ Net-_M3-Pad3_ Net-_M4-Pad3_ VDD GND Net-_M8-Pad3_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/ICS83840/ICS83840.cir.out b/library/SubcircuitLibrary/ICS83840/ICS83840.cir.out
new file mode 100644
index 000000000..6d8c549ea
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/ICS83840.cir.out
@@ -0,0 +1,126 @@
+* c:\fossee\esim\library\subcircuitlibrary\ics83840\ics83840.cir
+
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u6  net-_m6-pad2_ net-_u6-pad2_ adc_bridge_1
+* u8  net-_u6-pad2_ net-_u11-pad1_ d_inverter
+m4 hp0 net-_m4-pad2_ net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1
+m6 hp0 net-_m6-pad2_ net-_m4-pad3_ vdd CMOSP W=100u L=100u M=1
+m11 gnd net-_m11-pad2_ net-_m11-pad3_ gnd CMOSN W=100u L=100u M=1
+* u20  net-_u17-pad2_ net-_u20-pad2_ d_inverter
+* u11  net-_u11-pad1_ net-_m4-pad2_ dac_bridge_1
+* u17  net-_m4-pad2_ net-_u17-pad2_ adc_bridge_1
+* u22  net-_u20-pad2_ net-_m11-pad2_ dac_bridge_1
+r3  net-_m11-pad3_ net-_m4-pad3_ 20
+* u12  net-_m9-pad2_ net-_u12-pad2_ adc_bridge_1
+* u14  net-_u12-pad2_ net-_u14-pad2_ d_inverter
+m8 hp0 net-_m8-pad2_ net-_m8-pad3_ gnd CMOSN W=100u L=100u M=1
+m9 hp0 net-_m9-pad2_ net-_m8-pad3_ vdd CMOSP W=100u L=100u M=1
+m12 gnd net-_m12-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+* u24  net-_u23-pad2_ net-_u24-pad2_ d_inverter
+* u18  net-_u14-pad2_ net-_m8-pad2_ dac_bridge_1
+* u23  net-_m8-pad2_ net-_u23-pad2_ adc_bridge_1
+* u25  net-_u24-pad2_ net-_m12-pad2_ dac_bridge_1
+r4  net-_m12-pad3_ net-_m8-pad3_ 20
+* u5  net-_m5-pad2_ net-_u5-pad2_ adc_bridge_1
+* u7  net-_u5-pad2_ net-_u10-pad1_ d_inverter
+m3 hp0 net-_m3-pad2_ net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1
+m5 hp0 net-_m5-pad2_ net-_m3-pad3_ vdd CMOSP W=100u L=100u M=1
+m10 gnd net-_m10-pad2_ net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1
+* u19  net-_u16-pad2_ net-_u19-pad2_ d_inverter
+* u10  net-_u10-pad1_ net-_m3-pad2_ dac_bridge_1
+* u16  net-_m3-pad2_ net-_u16-pad2_ adc_bridge_1
+* u21  net-_u19-pad2_ net-_m10-pad2_ dac_bridge_1
+r2  net-_m10-pad3_ net-_m3-pad3_ 20
+* u2  net-_m2-pad2_ net-_u2-pad2_ adc_bridge_1
+* u3  net-_u2-pad2_ net-_u3-pad2_ d_inverter
+m1 hp0 net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m2 hp0 net-_m2-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+m7 gnd net-_m7-pad2_ net-_m7-pad3_ gnd CMOSN W=100u L=100u M=1
+* u13  net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u4  net-_u3-pad2_ net-_m1-pad2_ dac_bridge_1
+* u9  net-_m1-pad2_ net-_u13-pad1_ adc_bridge_1
+* u15  net-_u13-pad2_ net-_m7-pad2_ dac_bridge_1
+r1  net-_m7-pad3_ net-_m1-pad3_ 20
+* u1  net-_m2-pad2_ hp0 net-_m5-pad2_ net-_m6-pad2_ net-_m9-pad2_ net-_m1-pad3_ net-_m3-pad3_ net-_m4-pad3_ vdd gnd net-_m8-pad3_ port
+a1 [net-_m6-pad2_ ] [net-_u6-pad2_ ] u6
+a2 net-_u6-pad2_ net-_u11-pad1_ u8
+a3 net-_u17-pad2_ net-_u20-pad2_ u20
+a4 [net-_u11-pad1_ ] [net-_m4-pad2_ ] u11
+a5 [net-_m4-pad2_ ] [net-_u17-pad2_ ] u17
+a6 [net-_u20-pad2_ ] [net-_m11-pad2_ ] u22
+a7 [net-_m9-pad2_ ] [net-_u12-pad2_ ] u12
+a8 net-_u12-pad2_ net-_u14-pad2_ u14
+a9 net-_u23-pad2_ net-_u24-pad2_ u24
+a10 [net-_u14-pad2_ ] [net-_m8-pad2_ ] u18
+a11 [net-_m8-pad2_ ] [net-_u23-pad2_ ] u23
+a12 [net-_u24-pad2_ ] [net-_m12-pad2_ ] u25
+a13 [net-_m5-pad2_ ] [net-_u5-pad2_ ] u5
+a14 net-_u5-pad2_ net-_u10-pad1_ u7
+a15 net-_u16-pad2_ net-_u19-pad2_ u19
+a16 [net-_u10-pad1_ ] [net-_m3-pad2_ ] u10
+a17 [net-_m3-pad2_ ] [net-_u16-pad2_ ] u16
+a18 [net-_u19-pad2_ ] [net-_m10-pad2_ ] u21
+a19 [net-_m2-pad2_ ] [net-_u2-pad2_ ] u2
+a20 net-_u2-pad2_ net-_u3-pad2_ u3
+a21 net-_u13-pad1_ net-_u13-pad2_ u13
+a22 [net-_u3-pad2_ ] [net-_m1-pad2_ ] u4
+a23 [net-_m1-pad2_ ] [net-_u13-pad1_ ] u9
+a24 [net-_u13-pad2_ ] [net-_m7-pad2_ ] u15
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u23 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/ICS83840/ICS83840.pro b/library/SubcircuitLibrary/ICS83840/ICS83840.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/ICS83840.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/ICS83840/ICS83840.sch b/library/SubcircuitLibrary/ICS83840/ICS83840.sch
new file mode 100644
index 000000000..1c2230112
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/ICS83840.sch
@@ -0,0 +1,814 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:ICS83840_ckt-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+Date ""
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+Wire Wire Line
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+U 1 1 697C81E5
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+F 0 "U4" H 1350 8600 60  0000 C CNN
+F 1 "dac_bridge_1" H 1350 8750 60  0000 C CNN
+F 2 "" H 1350 8600 60  0000 C CNN
+F 3 "" H 1350 8600 60  0000 C CNN
+	1    1350 8600
+	1    0    0    -1  
+$EndComp
+$Comp
+L adc_bridge_1 U9
+U 1 1 697C81E6
+P 3050 8600
+F 0 "U9" H 3050 8600 60  0000 C CNN
+F 1 "adc_bridge_1" H 3050 8750 60  0000 C CNN
+F 2 "" H 3050 8600 60  0000 C CNN
+F 3 "" H 3050 8600 60  0000 C CNN
+	1    3050 8600
+	1    0    0    -1  
+$EndComp
+$Comp
+L dac_bridge_1 U15
+U 1 1 697C81E7
+P 5100 8600
+F 0 "U15" H 5100 8600 60  0000 C CNN
+F 1 "dac_bridge_1" H 5100 8750 60  0000 C CNN
+F 2 "" H 5100 8600 60  0000 C CNN
+F 3 "" H 5100 8600 60  0000 C CNN
+	1    5100 8600
+	1    0    0    -1  
+$EndComp
+Connection ~ 2250 8550
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	6250 8750 6000 8750
+Wire Wire Line
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+Wire Wire Line
+	-1050 8550 -1200 8550
+$Comp
+L resistor R1
+U 1 1 697C81E9
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+F 0 "R1" H 6100 8230 50  0000 C CNN
+F 1 "20" H 6100 8050 50  0000 C CNN
+F 2 "" H 6100 8080 30  0000 C CNN
+F 3 "" V 6100 8150 30  0000 C CNN
+	1    6050 8100
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Text GLabel 2400 7800 0    60   Input ~ 0
+VDD
+Text GLabel 650  5450 0    60   Input ~ 0
+HP0
+Text GLabel 4950 1450 0    60   Input ~ 0
+GND
+Wire Wire Line
+	8350 1100 4800 1100
+Wire Wire Line
+	10500 2950 6950 2950
+Wire Wire Line
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+Wire Wire Line
+	6000 7700 2450 7700
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+Text GLabel 6000 8750 0    60   Input ~ 0
+GND
+Text GLabel 8250 6300 0    60   Input ~ 0
+GND
+Text GLabel 10500 4000 0    60   Input ~ 0
+GND
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+GND
+Text GLabel 9950 1550 2    60   Input ~ 0
+GND
+Text GLabel 800  2400 2    60   Input ~ 0
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+$Comp
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+F 2 "" H 550 2400 60  0000 C CNN
+F 3 "" H 550 2400 60  0000 C CNN
+	2    550  2400
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 3 "" H 1050 1950 60  0000 C CNN
+	4    1050 1950
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+$EndComp
+$Comp
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+F 2 "" H 3200 3800 60  0000 C CNN
+F 3 "" H 3200 3800 60  0000 C CNN
+	5    3200 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 697D9245
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+F 1 "PORT" H 950 6100 30  0000 C CNN
+F 2 "" H 950 6100 60  0000 C CNN
+F 3 "" H 950 6100 60  0000 C CNN
+	3    950  6100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 697DA40E
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+F 2 "" H -1450 8550 60  0000 C CNN
+F 3 "" H -1450 8550 60  0000 C CNN
+	1    -1450 8550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
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+P 5750 7700
+F 0 "U1" H 5800 7800 30  0000 C CNN
+F 1 "PORT" H 5750 7700 30  0000 C CNN
+F 2 "" H 5750 7700 60  0000 C CNN
+F 3 "" H 5750 7700 60  0000 C CNN
+	6    5750 7700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 697DA51C
+P 8000 5250
+F 0 "U1" H 8050 5350 30  0000 C CNN
+F 1 "PORT" H 8000 5250 30  0000 C CNN
+F 2 "" H 8000 5250 60  0000 C CNN
+F 3 "" H 8000 5250 60  0000 C CNN
+	7    8000 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 697DC036
+P 10250 2950
+F 0 "U1" H 10300 3050 30  0000 C CNN
+F 1 "PORT" H 10250 2950 30  0000 C CNN
+F 2 "" H 10250 2950 60  0000 C CNN
+F 3 "" H 10250 2950 60  0000 C CNN
+	11   10250 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 697DC0BD
+P 8100 1100
+F 0 "U1" H 8150 1200 30  0000 C CNN
+F 1 "PORT" H 8100 1100 30  0000 C CNN
+F 2 "" H 8100 1100 60  0000 C CNN
+F 3 "" H 8100 1100 60  0000 C CNN
+	8    8100 1100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 697DC136
+P 9650 1000
+F 0 "U1" H 9700 1100 30  0000 C CNN
+F 1 "PORT" H 9650 1000 30  0000 C CNN
+F 2 "" H 9650 1000 60  0000 C CNN
+F 3 "" H 9650 1000 60  0000 C CNN
+	9    9650 1000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 697DC1BD
+P 9700 1550
+F 0 "U1" H 9750 1650 30  0000 C CNN
+F 1 "PORT" H 9700 1550 30  0000 C CNN
+F 2 "" H 9700 1550 60  0000 C CNN
+F 3 "" H 9700 1550 60  0000 C CNN
+	10   9700 1550
+	1    0    0    -1  
+$EndComp
+Text GLabel 4850 5600 0    60   Input ~ 0
+GND
+Text GLabel -1600 7900 0    60   Input ~ 0
+HP0
+Text GLabel 7100 3300 0    60   Input ~ 0
+GND
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/ICS83840/ICS83840.sub b/library/SubcircuitLibrary/ICS83840/ICS83840.sub
new file mode 100644
index 000000000..bd94e7365
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/ICS83840.sub
@@ -0,0 +1,120 @@
+* Subcircuit ICS83840
+.subckt ICS83840 net-_m2-pad2_ hp0 net-_m5-pad2_ net-_m6-pad2_ net-_m9-pad2_ net-_m1-pad3_ net-_m3-pad3_ net-_m4-pad3_ vdd gnd net-_m8-pad3_ 
+* c:\fossee\esim\library\subcircuitlibrary\ics83840\ics83840.cir
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u6  net-_m6-pad2_ net-_u6-pad2_ adc_bridge_1
+* u8  net-_u6-pad2_ net-_u11-pad1_ d_inverter
+m4 hp0 net-_m4-pad2_ net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1
+m6 hp0 net-_m6-pad2_ net-_m4-pad3_ vdd CMOSP W=100u L=100u M=1
+m11 gnd net-_m11-pad2_ net-_m11-pad3_ gnd CMOSN W=100u L=100u M=1
+* u20  net-_u17-pad2_ net-_u20-pad2_ d_inverter
+* u11  net-_u11-pad1_ net-_m4-pad2_ dac_bridge_1
+* u17  net-_m4-pad2_ net-_u17-pad2_ adc_bridge_1
+* u22  net-_u20-pad2_ net-_m11-pad2_ dac_bridge_1
+r3  net-_m11-pad3_ net-_m4-pad3_ 20
+* u12  net-_m9-pad2_ net-_u12-pad2_ adc_bridge_1
+* u14  net-_u12-pad2_ net-_u14-pad2_ d_inverter
+m8 hp0 net-_m8-pad2_ net-_m8-pad3_ gnd CMOSN W=100u L=100u M=1
+m9 hp0 net-_m9-pad2_ net-_m8-pad3_ vdd CMOSP W=100u L=100u M=1
+m12 gnd net-_m12-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+* u24  net-_u23-pad2_ net-_u24-pad2_ d_inverter
+* u18  net-_u14-pad2_ net-_m8-pad2_ dac_bridge_1
+* u23  net-_m8-pad2_ net-_u23-pad2_ adc_bridge_1
+* u25  net-_u24-pad2_ net-_m12-pad2_ dac_bridge_1
+r4  net-_m12-pad3_ net-_m8-pad3_ 20
+* u5  net-_m5-pad2_ net-_u5-pad2_ adc_bridge_1
+* u7  net-_u5-pad2_ net-_u10-pad1_ d_inverter
+m3 hp0 net-_m3-pad2_ net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1
+m5 hp0 net-_m5-pad2_ net-_m3-pad3_ vdd CMOSP W=100u L=100u M=1
+m10 gnd net-_m10-pad2_ net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1
+* u19  net-_u16-pad2_ net-_u19-pad2_ d_inverter
+* u10  net-_u10-pad1_ net-_m3-pad2_ dac_bridge_1
+* u16  net-_m3-pad2_ net-_u16-pad2_ adc_bridge_1
+* u21  net-_u19-pad2_ net-_m10-pad2_ dac_bridge_1
+r2  net-_m10-pad3_ net-_m3-pad3_ 20
+* u2  net-_m2-pad2_ net-_u2-pad2_ adc_bridge_1
+* u3  net-_u2-pad2_ net-_u3-pad2_ d_inverter
+m1 hp0 net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m2 hp0 net-_m2-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+m7 gnd net-_m7-pad2_ net-_m7-pad3_ gnd CMOSN W=100u L=100u M=1
+* u13  net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u4  net-_u3-pad2_ net-_m1-pad2_ dac_bridge_1
+* u9  net-_m1-pad2_ net-_u13-pad1_ adc_bridge_1
+* u15  net-_u13-pad2_ net-_m7-pad2_ dac_bridge_1
+r1  net-_m7-pad3_ net-_m1-pad3_ 20
+a1 [net-_m6-pad2_ ] [net-_u6-pad2_ ] u6
+a2 net-_u6-pad2_ net-_u11-pad1_ u8
+a3 net-_u17-pad2_ net-_u20-pad2_ u20
+a4 [net-_u11-pad1_ ] [net-_m4-pad2_ ] u11
+a5 [net-_m4-pad2_ ] [net-_u17-pad2_ ] u17
+a6 [net-_u20-pad2_ ] [net-_m11-pad2_ ] u22
+a7 [net-_m9-pad2_ ] [net-_u12-pad2_ ] u12
+a8 net-_u12-pad2_ net-_u14-pad2_ u14
+a9 net-_u23-pad2_ net-_u24-pad2_ u24
+a10 [net-_u14-pad2_ ] [net-_m8-pad2_ ] u18
+a11 [net-_m8-pad2_ ] [net-_u23-pad2_ ] u23
+a12 [net-_u24-pad2_ ] [net-_m12-pad2_ ] u25
+a13 [net-_m5-pad2_ ] [net-_u5-pad2_ ] u5
+a14 net-_u5-pad2_ net-_u10-pad1_ u7
+a15 net-_u16-pad2_ net-_u19-pad2_ u19
+a16 [net-_u10-pad1_ ] [net-_m3-pad2_ ] u10
+a17 [net-_m3-pad2_ ] [net-_u16-pad2_ ] u16
+a18 [net-_u19-pad2_ ] [net-_m10-pad2_ ] u21
+a19 [net-_m2-pad2_ ] [net-_u2-pad2_ ] u2
+a20 net-_u2-pad2_ net-_u3-pad2_ u3
+a21 net-_u13-pad1_ net-_u13-pad2_ u13
+a22 [net-_u3-pad2_ ] [net-_m1-pad2_ ] u4
+a23 [net-_m1-pad2_ ] [net-_u13-pad1_ ] u9
+a24 [net-_u13-pad2_ ] [net-_m7-pad2_ ] u15
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u23 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends ICS83840
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICS83840/ICS83840_Previous_Values.xml b/library/SubcircuitLibrary/ICS83840/ICS83840_Previous_Values.xml
new file mode 100644
index 000000000..6d2ef62f9
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/ICS83840_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u6 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u6><u8 name="type">d_inverter<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /></u8><u20 name="type">d_inverter<field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /><field10 name="Enter Input Load (default=1.0e-12)" /></u20><u11 name="type">dac_bridge<field11 name="Enter value for out_low (default=0.0)" /><field12 name="Enter value for out_high (default=5.0)" /><field13 name="Enter value for out_undef (default=0.5)" /><field14 name="Enter value for input load (default=1.0e-12)" /><field15 name="Enter the Rise Time (default=1.0e-9)" /><field16 name="Enter the Fall Time (default=1.0e-9)" /></u11><u17 name="type">adc_bridge<field17 name="Enter value for in_low (default=1.0)" /><field18 name="Enter value for in_high (default=2.0)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u17><u22 name="type">dac_bridge<field21 name="Enter value for out_low (default=0.0)" /><field22 name="Enter value for out_high (default=5.0)" /><field23 name="Enter value for out_undef (default=0.5)" /><field24 name="Enter value for input load (default=1.0e-12)" /><field25 name="Enter the Rise Time (default=1.0e-9)" /><field26 name="Enter the Fall Time (default=1.0e-9)" /></u22><u12 name="type">adc_bridge<field27 name="Enter value for in_low (default=1.0)" /><field28 name="Enter value for in_high (default=2.0)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u12><u14 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u14><u24 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u24><u18 name="type">dac_bridge<field37 name="Enter value for out_low (default=0.0)" /><field38 name="Enter value for out_high (default=5.0)" /><field39 name="Enter value for out_undef (default=0.5)" /><field40 name="Enter value for input load (default=1.0e-12)" /><field41 name="Enter the Rise Time (default=1.0e-9)" /><field42 name="Enter the Fall Time (default=1.0e-9)" /></u18><u23 name="type">adc_bridge<field43 name="Enter value for in_low (default=1.0)" /><field44 name="Enter value for in_high (default=2.0)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /><field46 name="Enter Fall Delay (default=1.0e-9)" /></u23><u25 name="type">dac_bridge<field47 name="Enter value for out_low (default=0.0)" /><field48 name="Enter value for out_high (default=5.0)" /><field49 name="Enter value for out_undef (default=0.5)" /><field50 name="Enter value for input load (default=1.0e-12)" /><field51 name="Enter the Rise Time (default=1.0e-9)" /><field52 name="Enter the Fall Time (default=1.0e-9)" /></u25><u5 name="type">adc_bridge<field53 name="Enter value for in_low (default=1.0)" /><field54 name="Enter value for in_high (default=2.0)" /><field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /></u5><u7 name="type">d_inverter<field57 name="Enter Rise Delay (default=1.0e-9)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /></u7><u19 name="type">d_inverter<field60 name="Enter Rise Delay (default=1.0e-9)" /><field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /></u19><u10 name="type">dac_bridge<field63 name="Enter value for out_low (default=0.0)" /><field64 name="Enter value for out_high (default=5.0)" /><field65 name="Enter value for out_undef (default=0.5)" /><field66 name="Enter value for input load (default=1.0e-12)" /><field67 name="Enter the Rise Time (default=1.0e-9)" /><field68 name="Enter the Fall Time (default=1.0e-9)" /></u10><u16 name="type">adc_bridge<field69 name="Enter value for in_low (default=1.0)" /><field70 name="Enter value for in_high (default=2.0)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /></u16><u21 name="type">dac_bridge<field73 name="Enter value for out_low (default=0.0)" /><field74 name="Enter value for out_high (default=5.0)" /><field75 name="Enter value for out_undef (default=0.5)" /><field76 name="Enter value for input load (default=1.0e-12)" /><field77 name="Enter the Rise Time (default=1.0e-9)" /><field78 name="Enter the Fall Time (default=1.0e-9)" /></u21><u2 name="type">adc_bridge<field79 name="Enter value for in_low (default=1.0)" /><field80 name="Enter value for in_high (default=2.0)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /><field82 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u3><u13 name="type">d_inverter<field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /></u13><u4 name="type">dac_bridge<field89 name="Enter value for out_low (default=0.0)" /><field90 name="Enter value for out_high (default=5.0)" /><field91 name="Enter value for out_undef (default=0.5)" /><field92 name="Enter value for input load (default=1.0e-12)" /><field93 name="Enter the Rise Time (default=1.0e-9)" /><field94 name="Enter the Fall Time (default=1.0e-9)" /></u4><u9 name="type">adc_bridge<field95 name="Enter value for in_low (default=1.0)" /><field96 name="Enter value for in_high (default=2.0)" /><field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /></u9><u15 name="type">dac_bridge<field99 name="Enter value for out_low (default=0.0)" /><field100 name="Enter value for out_high (default=5.0)" /><field101 name="Enter value for out_undef (default=0.5)" /><field102 name="Enter value for input load (default=1.0e-12)" /><field103 name="Enter the Rise Time (default=1.0e-9)" /><field104 name="Enter the Fall Time (default=1.0e-9)" /></u15></model><devicemodel><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m11><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m8><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m9><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m12><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m5><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m10><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m7></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICS83840/NMOS-180nm.lib b/library/SubcircuitLibrary/ICS83840/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/ICS83840/PMOS-180nm.lib b/library/SubcircuitLibrary/ICS83840/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/ICS83840/analysis b/library/SubcircuitLibrary/ICS83840/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/ICS83840/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/PI3B16244/NMOS-180nm.lib b/library/SubcircuitLibrary/PI3B16244/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/PI3B16244/PI3B16244-cache.lib b/library/SubcircuitLibrary/PI3B16244/PI3B16244-cache.lib
new file mode 100644
index 000000000..a55745972
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/PI3B16244-cache.lib
@@ -0,0 +1,142 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/PI3B16244/PI3B16244.cir b/library/SubcircuitLibrary/PI3B16244/PI3B16244.cir
new file mode 100644
index 000000000..12a35fc13
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/PI3B16244.cir
@@ -0,0 +1,92 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\PI3B16244\PI3B16244.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/30/26 19:37:26
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  1BE_B Net-_U1-Pad2_ adc_bridge_1		
+U5  Net-_U1-Pad2_ Net-_U5-Pad2_ d_inverter		
+M1  Net-_M1-Pad1_ 1BE_B Net-_M1-Pad3_ GND eSim_MOS_N		
+M5  Net-_M1-Pad1_ Net-_M5-Pad2_ Net-_M1-Pad3_ VDD eSim_MOS_P		
+U9  Net-_U5-Pad2_ Net-_M5-Pad2_ dac_bridge_1		
+U2  1BE_B Net-_U2-Pad2_ adc_bridge_1		
+U6  Net-_U2-Pad2_ Net-_U10-Pad1_ d_inverter		
+M2  Net-_M2-Pad1_ 1BE_B Net-_M2-Pad3_ GND eSim_MOS_N		
+M6  Net-_M2-Pad1_ Net-_M6-Pad2_ Net-_M2-Pad3_ VDD eSim_MOS_P		
+U10  Net-_U10-Pad1_ Net-_M6-Pad2_ dac_bridge_1		
+U3  1BE_B Net-_U3-Pad2_ adc_bridge_1		
+U7  Net-_U3-Pad2_ Net-_U11-Pad1_ d_inverter		
+M3  Net-_M3-Pad1_ 1BE_B Net-_M3-Pad3_ GND eSim_MOS_N		
+M7  Net-_M3-Pad1_ Net-_M7-Pad2_ Net-_M3-Pad3_ VDD eSim_MOS_P		
+U11  Net-_U11-Pad1_ Net-_M7-Pad2_ dac_bridge_1		
+U4  1BE_B Net-_U4-Pad2_ adc_bridge_1		
+U8  Net-_U4-Pad2_ Net-_U12-Pad1_ d_inverter		
+M4  Net-_M4-Pad1_ 1BE_B Net-_M4-Pad3_ GND eSim_MOS_N		
+M8  Net-_M4-Pad1_ Net-_M8-Pad2_ Net-_M4-Pad3_ VDD eSim_MOS_P		
+U12  Net-_U12-Pad1_ Net-_M8-Pad2_ dac_bridge_1		
+U26  3BE_B Net-_U26-Pad2_ adc_bridge_1		
+U30  Net-_U26-Pad2_ Net-_U30-Pad2_ d_inverter		
+M17  Net-_M17-Pad1_ 3BE_B Net-_M17-Pad3_ GND eSim_MOS_N		
+M21  Net-_M17-Pad1_ Net-_M21-Pad2_ Net-_M17-Pad3_ VDD eSim_MOS_P		
+U34  Net-_U30-Pad2_ Net-_M21-Pad2_ dac_bridge_1		
+U27  3BE_B Net-_U27-Pad2_ adc_bridge_1		
+U31  Net-_U27-Pad2_ Net-_U31-Pad2_ d_inverter		
+M18  Net-_M18-Pad1_ 3BE_B Net-_M18-Pad3_ GND eSim_MOS_N		
+M22  Net-_M18-Pad1_ Net-_M22-Pad2_ Net-_M18-Pad3_ VDD eSim_MOS_P		
+U35  Net-_U31-Pad2_ Net-_M22-Pad2_ dac_bridge_1		
+U28  3BE_B Net-_U28-Pad2_ adc_bridge_1		
+U32  Net-_U28-Pad2_ Net-_U32-Pad2_ d_inverter		
+M19  Net-_M19-Pad1_ 3BE_B Net-_M19-Pad3_ GND eSim_MOS_N		
+M23  Net-_M19-Pad1_ Net-_M23-Pad2_ Net-_M19-Pad3_ VDD eSim_MOS_P		
+U36  Net-_U32-Pad2_ Net-_M23-Pad2_ dac_bridge_1		
+U29  3BE_B Net-_U29-Pad2_ adc_bridge_1		
+U33  Net-_U29-Pad2_ Net-_U33-Pad2_ d_inverter		
+M20  Net-_M20-Pad1_ 3BE_B Net-_M20-Pad3_ GND eSim_MOS_N		
+M24  Net-_M20-Pad1_ Net-_M24-Pad2_ Net-_M20-Pad3_ VDD eSim_MOS_P		
+U37  Net-_U33-Pad2_ Net-_M24-Pad2_ dac_bridge_1		
+U14  2BE_B Net-_U14-Pad2_ adc_bridge_1		
+U18  Net-_U14-Pad2_ Net-_U18-Pad2_ d_inverter		
+M9  Net-_M13-Pad1_ 2BE_B Net-_M13-Pad3_ GND eSim_MOS_N		
+M13  Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M13-Pad3_ VDD eSim_MOS_P		
+U22  Net-_U18-Pad2_ Net-_M13-Pad2_ dac_bridge_1		
+U15  2BE_B Net-_U15-Pad2_ adc_bridge_1		
+U19  Net-_U15-Pad2_ Net-_U19-Pad2_ d_inverter		
+M10  Net-_M10-Pad1_ 2BE_B Net-_M10-Pad3_ GND eSim_MOS_N		
+M14  Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M10-Pad3_ VDD eSim_MOS_P		
+U23  Net-_U19-Pad2_ Net-_M14-Pad2_ dac_bridge_1		
+U16  2BE_B Net-_U16-Pad2_ adc_bridge_1		
+U20  Net-_U16-Pad2_ Net-_U20-Pad2_ d_inverter		
+M11  Net-_M11-Pad1_ 2BE_B Net-_M11-Pad3_ GND eSim_MOS_N		
+M15  Net-_M11-Pad1_ Net-_M15-Pad2_ Net-_M11-Pad3_ VDD eSim_MOS_P		
+U24  Net-_U20-Pad2_ Net-_M15-Pad2_ dac_bridge_1		
+U17  2BE_B Net-_U17-Pad2_ adc_bridge_1		
+U21  Net-_U17-Pad2_ Net-_U21-Pad2_ d_inverter		
+M12  Net-_M12-Pad1_ 2BE_B Net-_M12-Pad3_ GND eSim_MOS_N		
+M16  Net-_M12-Pad1_ Net-_M16-Pad2_ Net-_M12-Pad3_ VDD eSim_MOS_P		
+U25  Net-_U21-Pad2_ Net-_M16-Pad2_ dac_bridge_1		
+U39  4BE_B Net-_U39-Pad2_ adc_bridge_1		
+U44  Net-_U39-Pad2_ Net-_U44-Pad2_ d_inverter		
+M25  Net-_M25-Pad1_ 4BE_B Net-_M25-Pad3_ GND eSim_MOS_N		
+M29  Net-_M25-Pad1_ Net-_M29-Pad2_ Net-_M25-Pad3_ VDD eSim_MOS_P		
+U48  Net-_U44-Pad2_ Net-_M29-Pad2_ dac_bridge_1		
+U40  4BE_B Net-_U40-Pad2_ adc_bridge_1		
+U45  Net-_U40-Pad2_ Net-_U45-Pad2_ d_inverter		
+M26  Net-_M26-Pad1_ 4BE_B Net-_M26-Pad3_ GND eSim_MOS_N		
+M30  Net-_M26-Pad1_ Net-_M30-Pad2_ Net-_M26-Pad3_ VDD eSim_MOS_P		
+U49  Net-_U45-Pad2_ Net-_M30-Pad2_ dac_bridge_1		
+U41  4BE_B Net-_U41-Pad2_ adc_bridge_1		
+U46  Net-_U41-Pad2_ Net-_U46-Pad2_ d_inverter		
+M27  Net-_M27-Pad1_ 4BE_B Net-_M27-Pad3_ GND eSim_MOS_N		
+M31  Net-_M27-Pad1_ Net-_M31-Pad2_ Net-_M27-Pad3_ VDD eSim_MOS_P		
+U50  Net-_U46-Pad2_ Net-_M31-Pad2_ dac_bridge_1		
+U42  4BE_B Net-_U42-Pad2_ adc_bridge_1		
+U47  Net-_U42-Pad2_ Net-_U47-Pad2_ d_inverter		
+M28  Net-_M28-Pad1_ 4BE_B Net-_M28-Pad3_ GND eSim_MOS_N		
+M32  Net-_M28-Pad1_ Net-_M32-Pad2_ Net-_M28-Pad3_ VDD eSim_MOS_P		
+U51  Net-_U47-Pad2_ Net-_M32-Pad2_ dac_bridge_1		
+U13  Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M3-Pad1_ Net-_M4-Pad1_ Net-_M1-Pad3_ Net-_M2-Pad3_ Net-_M3-Pad3_ Net-_M4-Pad3_ 4BE_B VDD 3BE_B 2BE_B Net-_M13-Pad1_ Net-_M10-Pad1_ Net-_M11-Pad1_ Net-_M12-Pad1_ Net-_M13-Pad3_ Net-_M10-Pad3_ Net-_M11-Pad3_ Net-_M12-Pad3_ 1BE_B GND Net-_M17-Pad1_ Net-_M18-Pad1_ Net-_M19-Pad1_ Net-_M20-Pad1_ PORT		
+U38  Net-_M17-Pad3_ Net-_M18-Pad3_ Net-_M19-Pad3_ Net-_M20-Pad3_ Net-_M25-Pad1_ Net-_M26-Pad1_ Net-_M27-Pad1_ Net-_M28-Pad1_ Net-_M25-Pad3_ Net-_M26-Pad3_ Net-_M27-Pad3_ Net-_M28-Pad3_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/PI3B16244/PI3B16244.cir.out b/library/SubcircuitLibrary/PI3B16244/PI3B16244.cir.out
new file mode 100644
index 000000000..66b0a52f3
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/PI3B16244.cir.out
@@ -0,0 +1,239 @@
+* c:\fossee\esim\library\subcircuitlibrary\pi3b16244\pi3b16244.cir
+
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u1  1be_b net-_u1-pad2_ adc_bridge_1
+* u5  net-_u1-pad2_ net-_u5-pad2_ d_inverter
+m1 net-_m1-pad1_ 1be_b net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m5-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+* u9  net-_u5-pad2_ net-_m5-pad2_ dac_bridge_1
+* u2  1be_b net-_u2-pad2_ adc_bridge_1
+* u6  net-_u2-pad2_ net-_u10-pad1_ d_inverter
+m2 net-_m2-pad1_ 1be_b net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1
+m6 net-_m2-pad1_ net-_m6-pad2_ net-_m2-pad3_ vdd CMOSP W=100u L=100u M=1
+* u10  net-_u10-pad1_ net-_m6-pad2_ dac_bridge_1
+* u3  1be_b net-_u3-pad2_ adc_bridge_1
+* u7  net-_u3-pad2_ net-_u11-pad1_ d_inverter
+m3 net-_m3-pad1_ 1be_b net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1
+m7 net-_m3-pad1_ net-_m7-pad2_ net-_m3-pad3_ vdd CMOSP W=100u L=100u M=1
+* u11  net-_u11-pad1_ net-_m7-pad2_ dac_bridge_1
+* u4  1be_b net-_u4-pad2_ adc_bridge_1
+* u8  net-_u4-pad2_ net-_u12-pad1_ d_inverter
+m4 net-_m4-pad1_ 1be_b net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m4-pad1_ net-_m8-pad2_ net-_m4-pad3_ vdd CMOSP W=100u L=100u M=1
+* u12  net-_u12-pad1_ net-_m8-pad2_ dac_bridge_1
+* u26  3be_b net-_u26-pad2_ adc_bridge_1
+* u30  net-_u26-pad2_ net-_u30-pad2_ d_inverter
+m17 net-_m17-pad1_ 3be_b net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+m21 net-_m17-pad1_ net-_m21-pad2_ net-_m17-pad3_ vdd CMOSP W=100u L=100u M=1
+* u34  net-_u30-pad2_ net-_m21-pad2_ dac_bridge_1
+* u27  3be_b net-_u27-pad2_ adc_bridge_1
+* u31  net-_u27-pad2_ net-_u31-pad2_ d_inverter
+m18 net-_m18-pad1_ 3be_b net-_m18-pad3_ gnd CMOSN W=100u L=100u M=1
+m22 net-_m18-pad1_ net-_m22-pad2_ net-_m18-pad3_ vdd CMOSP W=100u L=100u M=1
+* u35  net-_u31-pad2_ net-_m22-pad2_ dac_bridge_1
+* u28  3be_b net-_u28-pad2_ adc_bridge_1
+* u32  net-_u28-pad2_ net-_u32-pad2_ d_inverter
+m19 net-_m19-pad1_ 3be_b net-_m19-pad3_ gnd CMOSN W=100u L=100u M=1
+m23 net-_m19-pad1_ net-_m23-pad2_ net-_m19-pad3_ vdd CMOSP W=100u L=100u M=1
+* u36  net-_u32-pad2_ net-_m23-pad2_ dac_bridge_1
+* u29  3be_b net-_u29-pad2_ adc_bridge_1
+* u33  net-_u29-pad2_ net-_u33-pad2_ d_inverter
+m20 net-_m20-pad1_ 3be_b net-_m20-pad3_ gnd CMOSN W=100u L=100u M=1
+m24 net-_m20-pad1_ net-_m24-pad2_ net-_m20-pad3_ vdd CMOSP W=100u L=100u M=1
+* u37  net-_u33-pad2_ net-_m24-pad2_ dac_bridge_1
+* u14  2be_b net-_u14-pad2_ adc_bridge_1
+* u18  net-_u14-pad2_ net-_u18-pad2_ d_inverter
+m9 net-_m13-pad1_ 2be_b net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m13-pad3_ vdd CMOSP W=100u L=100u M=1
+* u22  net-_u18-pad2_ net-_m13-pad2_ dac_bridge_1
+* u15  2be_b net-_u15-pad2_ adc_bridge_1
+* u19  net-_u15-pad2_ net-_u19-pad2_ d_inverter
+m10 net-_m10-pad1_ 2be_b net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1
+m14 net-_m10-pad1_ net-_m14-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+* u23  net-_u19-pad2_ net-_m14-pad2_ dac_bridge_1
+* u16  2be_b net-_u16-pad2_ adc_bridge_1
+* u20  net-_u16-pad2_ net-_u20-pad2_ d_inverter
+m11 net-_m11-pad1_ 2be_b net-_m11-pad3_ gnd CMOSN W=100u L=100u M=1
+m15 net-_m11-pad1_ net-_m15-pad2_ net-_m11-pad3_ vdd CMOSP W=100u L=100u M=1
+* u24  net-_u20-pad2_ net-_m15-pad2_ dac_bridge_1
+* u17  2be_b net-_u17-pad2_ adc_bridge_1
+* u21  net-_u17-pad2_ net-_u21-pad2_ d_inverter
+m12 net-_m12-pad1_ 2be_b net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m16 net-_m12-pad1_ net-_m16-pad2_ net-_m12-pad3_ vdd CMOSP W=100u L=100u M=1
+* u25  net-_u21-pad2_ net-_m16-pad2_ dac_bridge_1
+* u39  4be_b net-_u39-pad2_ adc_bridge_1
+* u44  net-_u39-pad2_ net-_u44-pad2_ d_inverter
+m25 net-_m25-pad1_ 4be_b net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m29 net-_m25-pad1_ net-_m29-pad2_ net-_m25-pad3_ vdd CMOSP W=100u L=100u M=1
+* u48  net-_u44-pad2_ net-_m29-pad2_ dac_bridge_1
+* u40  4be_b net-_u40-pad2_ adc_bridge_1
+* u45  net-_u40-pad2_ net-_u45-pad2_ d_inverter
+m26 net-_m26-pad1_ 4be_b net-_m26-pad3_ gnd CMOSN W=100u L=100u M=1
+m30 net-_m26-pad1_ net-_m30-pad2_ net-_m26-pad3_ vdd CMOSP W=100u L=100u M=1
+* u49  net-_u45-pad2_ net-_m30-pad2_ dac_bridge_1
+* u41  4be_b net-_u41-pad2_ adc_bridge_1
+* u46  net-_u41-pad2_ net-_u46-pad2_ d_inverter
+m27 net-_m27-pad1_ 4be_b net-_m27-pad3_ gnd CMOSN W=100u L=100u M=1
+m31 net-_m27-pad1_ net-_m31-pad2_ net-_m27-pad3_ vdd CMOSP W=100u L=100u M=1
+* u50  net-_u46-pad2_ net-_m31-pad2_ dac_bridge_1
+* u42  4be_b net-_u42-pad2_ adc_bridge_1
+* u47  net-_u42-pad2_ net-_u47-pad2_ d_inverter
+m28 net-_m28-pad1_ 4be_b net-_m28-pad3_ gnd CMOSN W=100u L=100u M=1
+m32 net-_m28-pad1_ net-_m32-pad2_ net-_m28-pad3_ vdd CMOSP W=100u L=100u M=1
+* u51  net-_u47-pad2_ net-_m32-pad2_ dac_bridge_1
+* u13  net-_m1-pad1_ net-_m2-pad1_ net-_m3-pad1_ net-_m4-pad1_ net-_m1-pad3_ net-_m2-pad3_ net-_m3-pad3_ net-_m4-pad3_ 4be_b vdd 3be_b 2be_b net-_m13-pad1_ net-_m10-pad1_ net-_m11-pad1_ net-_m12-pad1_ net-_m13-pad3_ net-_m10-pad3_ net-_m11-pad3_ net-_m12-pad3_ 1be_b gnd net-_m17-pad1_ net-_m18-pad1_ net-_m19-pad1_ net-_m20-pad1_ port
+* u38  net-_m17-pad3_ net-_m18-pad3_ net-_m19-pad3_ net-_m20-pad3_ net-_m25-pad1_ net-_m26-pad1_ net-_m27-pad1_ net-_m28-pad1_ net-_m25-pad3_ net-_m26-pad3_ net-_m27-pad3_ net-_m28-pad3_ port
+a1 [1be_b ] [net-_u1-pad2_ ] u1
+a2 net-_u1-pad2_ net-_u5-pad2_ u5
+a3 [net-_u5-pad2_ ] [net-_m5-pad2_ ] u9
+a4 [1be_b ] [net-_u2-pad2_ ] u2
+a5 net-_u2-pad2_ net-_u10-pad1_ u6
+a6 [net-_u10-pad1_ ] [net-_m6-pad2_ ] u10
+a7 [1be_b ] [net-_u3-pad2_ ] u3
+a8 net-_u3-pad2_ net-_u11-pad1_ u7
+a9 [net-_u11-pad1_ ] [net-_m7-pad2_ ] u11
+a10 [1be_b ] [net-_u4-pad2_ ] u4
+a11 net-_u4-pad2_ net-_u12-pad1_ u8
+a12 [net-_u12-pad1_ ] [net-_m8-pad2_ ] u12
+a13 [3be_b ] [net-_u26-pad2_ ] u26
+a14 net-_u26-pad2_ net-_u30-pad2_ u30
+a15 [net-_u30-pad2_ ] [net-_m21-pad2_ ] u34
+a16 [3be_b ] [net-_u27-pad2_ ] u27
+a17 net-_u27-pad2_ net-_u31-pad2_ u31
+a18 [net-_u31-pad2_ ] [net-_m22-pad2_ ] u35
+a19 [3be_b ] [net-_u28-pad2_ ] u28
+a20 net-_u28-pad2_ net-_u32-pad2_ u32
+a21 [net-_u32-pad2_ ] [net-_m23-pad2_ ] u36
+a22 [3be_b ] [net-_u29-pad2_ ] u29
+a23 net-_u29-pad2_ net-_u33-pad2_ u33
+a24 [net-_u33-pad2_ ] [net-_m24-pad2_ ] u37
+a25 [2be_b ] [net-_u14-pad2_ ] u14
+a26 net-_u14-pad2_ net-_u18-pad2_ u18
+a27 [net-_u18-pad2_ ] [net-_m13-pad2_ ] u22
+a28 [2be_b ] [net-_u15-pad2_ ] u15
+a29 net-_u15-pad2_ net-_u19-pad2_ u19
+a30 [net-_u19-pad2_ ] [net-_m14-pad2_ ] u23
+a31 [2be_b ] [net-_u16-pad2_ ] u16
+a32 net-_u16-pad2_ net-_u20-pad2_ u20
+a33 [net-_u20-pad2_ ] [net-_m15-pad2_ ] u24
+a34 [2be_b ] [net-_u17-pad2_ ] u17
+a35 net-_u17-pad2_ net-_u21-pad2_ u21
+a36 [net-_u21-pad2_ ] [net-_m16-pad2_ ] u25
+a37 [4be_b ] [net-_u39-pad2_ ] u39
+a38 net-_u39-pad2_ net-_u44-pad2_ u44
+a39 [net-_u44-pad2_ ] [net-_m29-pad2_ ] u48
+a40 [4be_b ] [net-_u40-pad2_ ] u40
+a41 net-_u40-pad2_ net-_u45-pad2_ u45
+a42 [net-_u45-pad2_ ] [net-_m30-pad2_ ] u49
+a43 [4be_b ] [net-_u41-pad2_ ] u41
+a44 net-_u41-pad2_ net-_u46-pad2_ u46
+a45 [net-_u46-pad2_ ] [net-_m31-pad2_ ] u50
+a46 [4be_b ] [net-_u42-pad2_ ] u42
+a47 net-_u42-pad2_ net-_u47-pad2_ u47
+a48 [net-_u47-pad2_ ] [net-_m32-pad2_ ] u51
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u26 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u27 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u28 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u36 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u29 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u37 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u39 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u48 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u40 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u49 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u41 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u50 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u42 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u51 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/PI3B16244/PI3B16244.pro b/library/SubcircuitLibrary/PI3B16244/PI3B16244.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/PI3B16244.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/PI3B16244/PI3B16244.sch b/library/SubcircuitLibrary/PI3B16244/PI3B16244.sch
new file mode 100644
index 000000000..f87b21970
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/PI3B16244.sch
@@ -0,0 +1,1767 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:PI3B16244-cache
+EELAYER 25 0
+EELAYER END
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+	6350 650  6300 650 
+Connection ~ 8250 1150
+$Comp
+L dac_bridge_1 U34
+U 1 1 697CBAB7
+P 7550 700
+F 0 "U34" H 7550 700 60  0000 C CNN
+F 1 "dac_bridge_1" H 7550 850 60  0000 C CNN
+F 2 "" H 7550 700 60  0000 C CNN
+F 3 "" H 7550 700 60  0000 C CNN
+	1    7550 700 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8100 650  8450 650 
+Wire Wire Line
+	8450 1600 5150 1600
+Connection ~ 5150 1600
+Connection ~ 8650 1100
+Text GLabel 8600 1050 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	5150 1600 5150 650 
+$Comp
+L adc_bridge_1 U27
+U 1 1 697CBABA
+P 5750 2100
+F 0 "U27" H 5750 2100 60  0000 C CNN
+F 1 "adc_bridge_1" H 5750 2250 60  0000 C CNN
+F 2 "" H 5750 2100 60  0000 C CNN
+F 3 "" H 5750 2100 60  0000 C CNN
+	1    5750 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U31
+U 1 1 697CBABB
+P 6650 2050
+F 0 "U31" H 6650 1950 60  0000 C CNN
+F 1 "d_inverter" H 6650 2200 60  0000 C CNN
+F 2 "" H 6700 2000 60  0000 C CNN
+F 3 "" H 6700 2000 60  0000 C CNN
+	1    6650 2050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M18
+U 1 1 697CBABC
+P 8250 2900
+F 0 "M18" H 8250 2750 50  0000 R CNN
+F 1 "eSim_MOS_N" H 8350 2850 50  0000 R CNN
+F 2 "" H 8550 2600 29  0000 C CNN
+F 3 "" H 8350 2700 60  0000 C CNN
+	1    8250 2900
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M22
+U 1 1 697CBABD
+P 8450 2200
+F 0 "M22" H 8400 2250 50  0000 R CNN
+F 1 "eSim_MOS_P" H 8500 2350 50  0000 R CNN
+F 2 "" H 8700 2300 29  0000 C CNN
+F 3 "" H 8500 2200 60  0000 C CNN
+	1    8450 2200
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	8250 2350 8250 2700
+Wire Wire Line
+	8650 2350 8650 2700
+Wire Wire Line
+	6350 2050 6300 2050
+Connection ~ 8250 2550
+$Comp
+L dac_bridge_1 U35
+U 1 1 697CBABE
+P 7550 2100
+F 0 "U35" H 7550 2100 60  0000 C CNN
+F 1 "dac_bridge_1" H 7550 2250 60  0000 C CNN
+F 2 "" H 7550 2100 60  0000 C CNN
+F 3 "" H 7550 2100 60  0000 C CNN
+	1    7550 2100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8100 2050 8450 2050
+Wire Wire Line
+	8450 3000 5150 3000
+Connection ~ 5150 3000
+Connection ~ 8650 2500
+Text GLabel 8600 2450 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	5150 3000 5150 2050
+$Comp
+L adc_bridge_1 U28
+U 1 1 697CBAC1
+P 5750 3500
+F 0 "U28" H 5750 3500 60  0000 C CNN
+F 1 "adc_bridge_1" H 5750 3650 60  0000 C CNN
+F 2 "" H 5750 3500 60  0000 C CNN
+F 3 "" H 5750 3500 60  0000 C CNN
+	1    5750 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U32
+U 1 1 697CBAC2
+P 6650 3450
+F 0 "U32" H 6650 3350 60  0000 C CNN
+F 1 "d_inverter" H 6650 3600 60  0000 C CNN
+F 2 "" H 6700 3400 60  0000 C CNN
+F 3 "" H 6700 3400 60  0000 C CNN
+	1    6650 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M19
+U 1 1 697CBAC3
+P 8250 4300
+F 0 "M19" H 8250 4150 50  0000 R CNN
+F 1 "eSim_MOS_N" H 8350 4250 50  0000 R CNN
+F 2 "" H 8550 4000 29  0000 C CNN
+F 3 "" H 8350 4100 60  0000 C CNN
+	1    8250 4300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M23
+U 1 1 697CBAC4
+P 8450 3600
+F 0 "M23" H 8400 3650 50  0000 R CNN
+F 1 "eSim_MOS_P" H 8500 3750 50  0000 R CNN
+F 2 "" H 8700 3700 29  0000 C CNN
+F 3 "" H 8500 3600 60  0000 C CNN
+	1    8450 3600
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	8250 3750 8250 4100
+Wire Wire Line
+	8650 3750 8650 4100
+Wire Wire Line
+	6350 3450 6300 3450
+Connection ~ 8250 3950
+$Comp
+L dac_bridge_1 U36
+U 1 1 697CBAC5
+P 7550 3500
+F 0 "U36" H 7550 3500 60  0000 C CNN
+F 1 "dac_bridge_1" H 7550 3650 60  0000 C CNN
+F 2 "" H 7550 3500 60  0000 C CNN
+F 3 "" H 7550 3500 60  0000 C CNN
+	1    7550 3500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8100 3450 8450 3450
+Wire Wire Line
+	8450 4400 5150 4400
+Connection ~ 5150 4400
+Connection ~ 8650 3900
+Text GLabel 8600 3850 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	5150 4400 5150 3450
+$Comp
+L adc_bridge_1 U29
+U 1 1 697CBAC8
+P 5750 4900
+F 0 "U29" H 5750 4900 60  0000 C CNN
+F 1 "adc_bridge_1" H 5750 5050 60  0000 C CNN
+F 2 "" H 5750 4900 60  0000 C CNN
+F 3 "" H 5750 4900 60  0000 C CNN
+	1    5750 4900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U33
+U 1 1 697CBAC9
+P 6650 4850
+F 0 "U33" H 6650 4750 60  0000 C CNN
+F 1 "d_inverter" H 6650 5000 60  0000 C CNN
+F 2 "" H 6700 4800 60  0000 C CNN
+F 3 "" H 6700 4800 60  0000 C CNN
+	1    6650 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M20
+U 1 1 697CBACA
+P 8250 5700
+F 0 "M20" H 8250 5550 50  0000 R CNN
+F 1 "eSim_MOS_N" H 8350 5650 50  0000 R CNN
+F 2 "" H 8550 5400 29  0000 C CNN
+F 3 "" H 8350 5500 60  0000 C CNN
+	1    8250 5700
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M24
+U 1 1 697CBACB
+P 8450 5000
+F 0 "M24" H 8400 5050 50  0000 R CNN
+F 1 "eSim_MOS_P" H 8500 5150 50  0000 R CNN
+F 2 "" H 8700 5100 29  0000 C CNN
+F 3 "" H 8500 5000 60  0000 C CNN
+	1    8450 5000
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	8250 5150 8250 5500
+Wire Wire Line
+	8650 5150 8650 5500
+Wire Wire Line
+	6350 4850 6300 4850
+Connection ~ 8250 5350
+$Comp
+L dac_bridge_1 U37
+U 1 1 697CBACC
+P 7550 4900
+F 0 "U37" H 7550 4900 60  0000 C CNN
+F 1 "dac_bridge_1" H 7550 5050 60  0000 C CNN
+F 2 "" H 7550 4900 60  0000 C CNN
+F 3 "" H 7550 4900 60  0000 C CNN
+	1    7550 4900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8100 4850 8450 4850
+Wire Wire Line
+	8450 5800 5150 5800
+Connection ~ 5150 5800
+Connection ~ 8650 5300
+Text GLabel 8600 5250 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	5150 5800 5150 4850
+Text GLabel 950  1800 0    60   Input ~ 0
+2BE_B
+$Comp
+L adc_bridge_1 U14
+U 1 1 697CBAED
+P 1550 900
+F 0 "U14" H 1550 900 60  0000 C CNN
+F 1 "adc_bridge_1" H 1550 1050 60  0000 C CNN
+F 2 "" H 1550 900 60  0000 C CNN
+F 3 "" H 1550 900 60  0000 C CNN
+	1    1550 900 
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U18
+U 1 1 697CBAEE
+P 2450 850
+F 0 "U18" H 2450 750 60  0000 C CNN
+F 1 "d_inverter" H 2450 1000 60  0000 C CNN
+F 2 "" H 2500 800 60  0000 C CNN
+F 3 "" H 2500 800 60  0000 C CNN
+	1    2450 850 
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M9
+U 1 1 697CBAEF
+P 4050 1700
+F 0 "M9" H 4050 1550 50  0000 R CNN
+F 1 "eSim_MOS_N" H 4150 1650 50  0000 R CNN
+F 2 "" H 4350 1400 29  0000 C CNN
+F 3 "" H 4150 1500 60  0000 C CNN
+	1    4050 1700
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M13
+U 1 1 697CBAF0
+P 4250 1000
+F 0 "M13" H 4200 1050 50  0000 R CNN
+F 1 "eSim_MOS_P" H 4300 1150 50  0000 R CNN
+F 2 "" H 4500 1100 29  0000 C CNN
+F 3 "" H 4300 1000 60  0000 C CNN
+	1    4250 1000
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	4050 1150 4050 1500
+Wire Wire Line
+	4450 1150 4450 1500
+Wire Wire Line
+	2150 850  2100 850 
+Connection ~ 4050 1350
+$Comp
+L dac_bridge_1 U22
+U 1 1 697CBAF1
+P 3350 900
+F 0 "U22" H 3350 900 60  0000 C CNN
+F 1 "dac_bridge_1" H 3350 1050 60  0000 C CNN
+F 2 "" H 3350 900 60  0000 C CNN
+F 3 "" H 3350 900 60  0000 C CNN
+	1    3350 900 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3900 850  4250 850 
+Wire Wire Line
+	4250 1800 950  1800
+Connection ~ 950  1800
+Connection ~ 4450 1300
+Text GLabel 4400 1250 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	950  1800 950  850 
+$Comp
+L adc_bridge_1 U15
+U 1 1 697CBAF4
+P 1550 2300
+F 0 "U15" H 1550 2300 60  0000 C CNN
+F 1 "adc_bridge_1" H 1550 2450 60  0000 C CNN
+F 2 "" H 1550 2300 60  0000 C CNN
+F 3 "" H 1550 2300 60  0000 C CNN
+	1    1550 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U19
+U 1 1 697CBAF5
+P 2450 2250
+F 0 "U19" H 2450 2150 60  0000 C CNN
+F 1 "d_inverter" H 2450 2400 60  0000 C CNN
+F 2 "" H 2500 2200 60  0000 C CNN
+F 3 "" H 2500 2200 60  0000 C CNN
+	1    2450 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 697CBAF6
+P 4050 3100
+F 0 "M10" H 4050 2950 50  0000 R CNN
+F 1 "eSim_MOS_N" H 4150 3050 50  0000 R CNN
+F 2 "" H 4350 2800 29  0000 C CNN
+F 3 "" H 4150 2900 60  0000 C CNN
+	1    4050 3100
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M14
+U 1 1 697CBAF7
+P 4250 2400
+F 0 "M14" H 4200 2450 50  0000 R CNN
+F 1 "eSim_MOS_P" H 4300 2550 50  0000 R CNN
+F 2 "" H 4500 2500 29  0000 C CNN
+F 3 "" H 4300 2400 60  0000 C CNN
+	1    4250 2400
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	4050 2550 4050 2900
+Wire Wire Line
+	4450 2550 4450 2900
+Wire Wire Line
+	2150 2250 2100 2250
+Connection ~ 4050 2750
+$Comp
+L dac_bridge_1 U23
+U 1 1 697CBAF8
+P 3350 2300
+F 0 "U23" H 3350 2300 60  0000 C CNN
+F 1 "dac_bridge_1" H 3350 2450 60  0000 C CNN
+F 2 "" H 3350 2300 60  0000 C CNN
+F 3 "" H 3350 2300 60  0000 C CNN
+	1    3350 2300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3900 2250 4250 2250
+Wire Wire Line
+	4250 3200 950  3200
+Connection ~ 950  3200
+Connection ~ 4450 2700
+Text GLabel 4400 2650 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	950  3200 950  2250
+$Comp
+L adc_bridge_1 U16
+U 1 1 697CBAFB
+P 1550 3700
+F 0 "U16" H 1550 3700 60  0000 C CNN
+F 1 "adc_bridge_1" H 1550 3850 60  0000 C CNN
+F 2 "" H 1550 3700 60  0000 C CNN
+F 3 "" H 1550 3700 60  0000 C CNN
+	1    1550 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U20
+U 1 1 697CBAFC
+P 2450 3650
+F 0 "U20" H 2450 3550 60  0000 C CNN
+F 1 "d_inverter" H 2450 3800 60  0000 C CNN
+F 2 "" H 2500 3600 60  0000 C CNN
+F 3 "" H 2500 3600 60  0000 C CNN
+	1    2450 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M11
+U 1 1 697CBAFD
+P 4050 4500
+F 0 "M11" H 4050 4350 50  0000 R CNN
+F 1 "eSim_MOS_N" H 4150 4450 50  0000 R CNN
+F 2 "" H 4350 4200 29  0000 C CNN
+F 3 "" H 4150 4300 60  0000 C CNN
+	1    4050 4500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M15
+U 1 1 697CBAFE
+P 4250 3800
+F 0 "M15" H 4200 3850 50  0000 R CNN
+F 1 "eSim_MOS_P" H 4300 3950 50  0000 R CNN
+F 2 "" H 4500 3900 29  0000 C CNN
+F 3 "" H 4300 3800 60  0000 C CNN
+	1    4250 3800
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	4050 3950 4050 4300
+Wire Wire Line
+	4450 3950 4450 4300
+Wire Wire Line
+	2150 3650 2100 3650
+Connection ~ 4050 4150
+$Comp
+L dac_bridge_1 U24
+U 1 1 697CBAFF
+P 3350 3700
+F 0 "U24" H 3350 3700 60  0000 C CNN
+F 1 "dac_bridge_1" H 3350 3850 60  0000 C CNN
+F 2 "" H 3350 3700 60  0000 C CNN
+F 3 "" H 3350 3700 60  0000 C CNN
+	1    3350 3700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3900 3650 4250 3650
+Wire Wire Line
+	4250 4600 950  4600
+Connection ~ 950  4600
+Connection ~ 4450 4100
+Text GLabel 4400 4050 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	950  4600 950  3650
+$Comp
+L adc_bridge_1 U17
+U 1 1 697CBB02
+P 1550 5100
+F 0 "U17" H 1550 5100 60  0000 C CNN
+F 1 "adc_bridge_1" H 1550 5250 60  0000 C CNN
+F 2 "" H 1550 5100 60  0000 C CNN
+F 3 "" H 1550 5100 60  0000 C CNN
+	1    1550 5100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 697CBB03
+P 2450 5050
+F 0 "U21" H 2450 4950 60  0000 C CNN
+F 1 "d_inverter" H 2450 5200 60  0000 C CNN
+F 2 "" H 2500 5000 60  0000 C CNN
+F 3 "" H 2500 5000 60  0000 C CNN
+	1    2450 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M12
+U 1 1 697CBB04
+P 4050 5900
+F 0 "M12" H 4050 5750 50  0000 R CNN
+F 1 "eSim_MOS_N" H 4150 5850 50  0000 R CNN
+F 2 "" H 4350 5600 29  0000 C CNN
+F 3 "" H 4150 5700 60  0000 C CNN
+	1    4050 5900
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M16
+U 1 1 697CBB05
+P 4250 5200
+F 0 "M16" H 4200 5250 50  0000 R CNN
+F 1 "eSim_MOS_P" H 4300 5350 50  0000 R CNN
+F 2 "" H 4500 5300 29  0000 C CNN
+F 3 "" H 4300 5200 60  0000 C CNN
+	1    4250 5200
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	4050 5350 4050 5700
+Wire Wire Line
+	4450 5350 4450 5700
+Wire Wire Line
+	2150 5050 2100 5050
+Connection ~ 4050 5550
+$Comp
+L dac_bridge_1 U25
+U 1 1 697CBB06
+P 3350 5100
+F 0 "U25" H 3350 5100 60  0000 C CNN
+F 1 "dac_bridge_1" H 3350 5250 60  0000 C CNN
+F 2 "" H 3350 5100 60  0000 C CNN
+F 3 "" H 3350 5100 60  0000 C CNN
+	1    3350 5100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3900 5050 4250 5050
+Wire Wire Line
+	4250 6000 950  6000
+Connection ~ 950  6000
+Connection ~ 4450 5500
+Text GLabel 4400 5450 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	950  6000 950  5050
+Text GLabel 9500 1750 0    60   Input ~ 0
+4BE_B
+$Comp
+L adc_bridge_1 U39
+U 1 1 697CBB09
+P 10100 850
+F 0 "U39" H 10100 850 60  0000 C CNN
+F 1 "adc_bridge_1" H 10100 1000 60  0000 C CNN
+F 2 "" H 10100 850 60  0000 C CNN
+F 3 "" H 10100 850 60  0000 C CNN
+	1    10100 850 
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U44
+U 1 1 697CBB0A
+P 11000 800
+F 0 "U44" H 11000 700 60  0000 C CNN
+F 1 "d_inverter" H 11000 950 60  0000 C CNN
+F 2 "" H 11050 750 60  0000 C CNN
+F 3 "" H 11050 750 60  0000 C CNN
+	1    11000 800 
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M25
+U 1 1 697CBB0B
+P 12600 1650
+F 0 "M25" H 12600 1500 50  0000 R CNN
+F 1 "eSim_MOS_N" H 12700 1600 50  0000 R CNN
+F 2 "" H 12900 1350 29  0000 C CNN
+F 3 "" H 12700 1450 60  0000 C CNN
+	1    12600 1650
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M29
+U 1 1 697CBB0C
+P 12800 950
+F 0 "M29" H 12750 1000 50  0000 R CNN
+F 1 "eSim_MOS_P" H 12850 1100 50  0000 R CNN
+F 2 "" H 13050 1050 29  0000 C CNN
+F 3 "" H 12850 950 60  0000 C CNN
+	1    12800 950 
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	12600 1100 12600 1450
+Wire Wire Line
+	13000 1100 13000 1450
+Wire Wire Line
+	10700 800  10650 800 
+Connection ~ 12600 1300
+$Comp
+L dac_bridge_1 U48
+U 1 1 697CBB0D
+P 11900 850
+F 0 "U48" H 11900 850 60  0000 C CNN
+F 1 "dac_bridge_1" H 11900 1000 60  0000 C CNN
+F 2 "" H 11900 850 60  0000 C CNN
+F 3 "" H 11900 850 60  0000 C CNN
+	1    11900 850 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12450 800  12800 800 
+Wire Wire Line
+	12800 1750 9500 1750
+Connection ~ 9500 1750
+Connection ~ 13000 1250
+Text GLabel 12950 1200 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	9500 1750 9500 800 
+Text GLabel 9500 3150 0    60   Input ~ 0
+4BE_B
+$Comp
+L adc_bridge_1 U40
+U 1 1 697CBB10
+P 10100 2250
+F 0 "U40" H 10100 2250 60  0000 C CNN
+F 1 "adc_bridge_1" H 10100 2400 60  0000 C CNN
+F 2 "" H 10100 2250 60  0000 C CNN
+F 3 "" H 10100 2250 60  0000 C CNN
+	1    10100 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U45
+U 1 1 697CBB11
+P 11000 2200
+F 0 "U45" H 11000 2100 60  0000 C CNN
+F 1 "d_inverter" H 11000 2350 60  0000 C CNN
+F 2 "" H 11050 2150 60  0000 C CNN
+F 3 "" H 11050 2150 60  0000 C CNN
+	1    11000 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M26
+U 1 1 697CBB12
+P 12600 3050
+F 0 "M26" H 12600 2900 50  0000 R CNN
+F 1 "eSim_MOS_N" H 12700 3000 50  0000 R CNN
+F 2 "" H 12900 2750 29  0000 C CNN
+F 3 "" H 12700 2850 60  0000 C CNN
+	1    12600 3050
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M30
+U 1 1 697CBB13
+P 12800 2350
+F 0 "M30" H 12750 2400 50  0000 R CNN
+F 1 "eSim_MOS_P" H 12850 2500 50  0000 R CNN
+F 2 "" H 13050 2450 29  0000 C CNN
+F 3 "" H 12850 2350 60  0000 C CNN
+	1    12800 2350
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	12600 2500 12600 2850
+Wire Wire Line
+	13000 2500 13000 2850
+Wire Wire Line
+	10700 2200 10650 2200
+Connection ~ 12600 2700
+$Comp
+L dac_bridge_1 U49
+U 1 1 697CBB14
+P 11900 2250
+F 0 "U49" H 11900 2250 60  0000 C CNN
+F 1 "dac_bridge_1" H 11900 2400 60  0000 C CNN
+F 2 "" H 11900 2250 60  0000 C CNN
+F 3 "" H 11900 2250 60  0000 C CNN
+	1    11900 2250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12450 2200 12800 2200
+Wire Wire Line
+	12800 3150 9500 3150
+Connection ~ 9500 3150
+Connection ~ 13000 2650
+Text GLabel 12950 2600 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	9500 3150 9500 2200
+Text GLabel 9500 4550 0    60   Input ~ 0
+4BE_B
+$Comp
+L adc_bridge_1 U41
+U 1 1 697CBB17
+P 10100 3650
+F 0 "U41" H 10100 3650 60  0000 C CNN
+F 1 "adc_bridge_1" H 10100 3800 60  0000 C CNN
+F 2 "" H 10100 3650 60  0000 C CNN
+F 3 "" H 10100 3650 60  0000 C CNN
+	1    10100 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U46
+U 1 1 697CBB18
+P 11000 3600
+F 0 "U46" H 11000 3500 60  0000 C CNN
+F 1 "d_inverter" H 11000 3750 60  0000 C CNN
+F 2 "" H 11050 3550 60  0000 C CNN
+F 3 "" H 11050 3550 60  0000 C CNN
+	1    11000 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M27
+U 1 1 697CBB19
+P 12600 4450
+F 0 "M27" H 12600 4300 50  0000 R CNN
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+	0    -1   -1   0   
+$EndComp
+$Comp
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+F 3 "" H 12850 3750 60  0000 C CNN
+	1    12800 3750
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	13000 3900 13000 4250
+Wire Wire Line
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+F 0 "U50" H 11900 3650 60  0000 C CNN
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+F 2 "" H 11900 3650 60  0000 C CNN
+F 3 "" H 11900 3650 60  0000 C CNN
+	1    11900 3650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12450 3600 12800 3600
+Wire Wire Line
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+Connection ~ 9500 4550
+Connection ~ 13000 4050
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+Wire Wire Line
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+F 3 "" H 10100 5050 60  0000 C CNN
+	1    10100 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U47
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+F 2 "" H 11050 4950 60  0000 C CNN
+F 3 "" H 11050 4950 60  0000 C CNN
+	1    11000 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M28
+U 1 1 697CBB20
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+F 2 "" H 12900 5550 29  0000 C CNN
+F 3 "" H 12700 5650 60  0000 C CNN
+	1    12600 5850
+	0    -1   -1   0   
+$EndComp
+$Comp
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+F 2 "" H 13050 5250 29  0000 C CNN
+F 3 "" H 12850 5150 60  0000 C CNN
+	1    12800 5150
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	12600 5300 12600 5650
+Wire Wire Line
+	13000 5300 13000 5650
+Wire Wire Line
+	10700 5000 10650 5000
+Connection ~ 12600 5500
+$Comp
+L dac_bridge_1 U51
+U 1 1 697CBB22
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+F 1 "dac_bridge_1" H 11900 5200 60  0000 C CNN
+F 2 "" H 11900 5050 60  0000 C CNN
+F 3 "" H 11900 5050 60  0000 C CNN
+	1    11900 5050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12450 5000 12800 5000
+Wire Wire Line
+	12800 5950 9500 5950
+Connection ~ 9500 5950
+Connection ~ 13000 5450
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+Wire Wire Line
+	9500 5950 9500 5000
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+3BE_B
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+$Comp
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+F 1 "PORT" H -150 1450 30  0000 C CNN
+F 2 "" H -150 1450 60  0000 C CNN
+F 3 "" H -150 1450 60  0000 C CNN
+	5    -150 1450
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+$EndComp
+$Comp
+L PORT U13
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+F 0 "U13" H -100 2950 30  0000 C CNN
+F 1 "PORT" H -150 2850 30  0000 C CNN
+F 2 "" H -150 2850 60  0000 C CNN
+F 3 "" H -150 2850 60  0000 C CNN
+	6    -150 2850
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 7 1 697D8B6B
+P -150 4250
+F 0 "U13" H -100 4350 30  0000 C CNN
+F 1 "PORT" H -150 4250 30  0000 C CNN
+F 2 "" H -150 4250 60  0000 C CNN
+F 3 "" H -150 4250 60  0000 C CNN
+	7    -150 4250
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 8 1 697D9D47
+P -150 5650
+F 0 "U13" H -100 5750 30  0000 C CNN
+F 1 "PORT" H -150 5650 30  0000 C CNN
+F 2 "" H -150 5650 60  0000 C CNN
+F 3 "" H -150 5650 60  0000 C CNN
+	8    -150 5650
+	-1   0    0    -1  
+$EndComp
+Text GLabel -3900 1950 0    60   Input ~ 0
+1BE_B
+Text GLabel 4050 250  2    60   Input ~ 0
+2BE_B
+Text GLabel -3900 3350 0    60   Input ~ 0
+1BE_B
+Text GLabel -3900 4750 0    60   Input ~ 0
+1BE_B
+Text GLabel -3900 6150 0    60   Input ~ 0
+1BE_B
+Text GLabel 5200 250  2    60   Input ~ 0
+1BE_B
+$Comp
+L PORT U13
+U 1 1 697ECE79
+P -1050 1500
+F 0 "U13" H -1000 1600 30  0000 C CNN
+F 1 "PORT" H -1050 1500 30  0000 C CNN
+F 2 "" H -1050 1500 60  0000 C CNN
+F 3 "" H -1050 1500 60  0000 C CNN
+	1    -1050 1500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 2 1 697EEC57
+P -1050 2900
+F 0 "U13" H -1000 3000 30  0000 C CNN
+F 1 "PORT" H -1050 2900 30  0000 C CNN
+F 2 "" H -1050 2900 60  0000 C CNN
+F 3 "" H -1050 2900 60  0000 C CNN
+	2    -1050 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 3 1 697EED3C
+P -1050 4300
+F 0 "U13" H -1000 4400 30  0000 C CNN
+F 1 "PORT" H -1050 4300 30  0000 C CNN
+F 2 "" H -1050 4300 60  0000 C CNN
+F 3 "" H -1050 4300 60  0000 C CNN
+	3    -1050 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 4 1 697F0C19
+P -1050 5700
+F 0 "U13" H -1000 5800 30  0000 C CNN
+F 1 "PORT" H -1050 5700 30  0000 C CNN
+F 2 "" H -1050 5700 60  0000 C CNN
+F 3 "" H -1050 5700 60  0000 C CNN
+	4    -1050 5700
+	1    0    0    -1  
+$EndComp
+Text GLabel -100 1800 0    60   Input ~ 0
+GND
+Wire Wire Line
+	-450 1550 -100 1550
+Wire Wire Line
+	-100 1550 -100 1800
+Text GLabel -100 3200 0    60   Input ~ 0
+GND
+Wire Wire Line
+	-450 2950 -100 2950
+Wire Wire Line
+	-100 2950 -100 3200
+Text GLabel -100 4600 0    60   Input ~ 0
+GND
+Wire Wire Line
+	-450 4350 -100 4350
+Wire Wire Line
+	-100 4350 -100 4600
+Text GLabel -100 6000 0    60   Input ~ 0
+GND
+Wire Wire Line
+	-450 5750 -100 5750
+Wire Wire Line
+	-100 5750 -100 6000
+Text GLabel 2800 250  2    60   Input ~ 0
+3BE_B
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+4BE_B
+$Comp
+L PORT U38
+U 9 1 698158CE
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+F 1 "PORT" H 13250 1250 30  0000 C CNN
+F 2 "" H 13250 1250 60  0000 C CNN
+F 3 "" H 13250 1250 60  0000 C CNN
+	9    13250 1250
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U38
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+F 0 "U38" H 13300 2750 30  0000 C CNN
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+F 2 "" H 13250 2650 60  0000 C CNN
+F 3 "" H 13250 2650 60  0000 C CNN
+	10   13250 2650
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U38
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+F 0 "U38" H 13300 4150 30  0000 C CNN
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+F 2 "" H 13250 4050 60  0000 C CNN
+F 3 "" H 13250 4050 60  0000 C CNN
+	11   13250 4050
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U38
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+F 2 "" H 13250 5450 60  0000 C CNN
+F 3 "" H 13250 5450 60  0000 C CNN
+	12   13250 5450
+	-1   0    0    -1  
+$EndComp
+Text GLabel 13300 1600 0    60   Input ~ 0
+GND
+Wire Wire Line
+	12950 1350 13300 1350
+Wire Wire Line
+	13300 1350 13300 1600
+Text GLabel 13300 3000 0    60   Input ~ 0
+GND
+Wire Wire Line
+	12950 2750 13300 2750
+Wire Wire Line
+	13300 2750 13300 3000
+Text GLabel 13300 4400 0    60   Input ~ 0
+GND
+Wire Wire Line
+	12950 4150 13300 4150
+Wire Wire Line
+	13300 4150 13300 4400
+Text GLabel 13300 5800 0    60   Input ~ 0
+GND
+Wire Wire Line
+	12950 5550 13300 5550
+Wire Wire Line
+	13300 5550 13300 5800
+$Comp
+L PORT U38
+U 1 1 698162AA
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+F 0 "U38" H 8950 1200 30  0000 C CNN
+F 1 "PORT" H 8900 1100 30  0000 C CNN
+F 2 "" H 8900 1100 60  0000 C CNN
+F 3 "" H 8900 1100 60  0000 C CNN
+	1    8900 1100
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U38
+U 2 1 698162B0
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+F 0 "U38" H 8950 2600 30  0000 C CNN
+F 1 "PORT" H 8900 2500 30  0000 C CNN
+F 2 "" H 8900 2500 60  0000 C CNN
+F 3 "" H 8900 2500 60  0000 C CNN
+	2    8900 2500
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U38
+U 3 1 698162B6
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+F 0 "U38" H 8950 4000 30  0000 C CNN
+F 1 "PORT" H 8900 3900 30  0000 C CNN
+F 2 "" H 8900 3900 60  0000 C CNN
+F 3 "" H 8900 3900 60  0000 C CNN
+	3    8900 3900
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U38
+U 4 1 698162BC
+P 8900 5300
+F 0 "U38" H 8950 5400 30  0000 C CNN
+F 1 "PORT" H 8900 5300 30  0000 C CNN
+F 2 "" H 8900 5300 60  0000 C CNN
+F 3 "" H 8900 5300 60  0000 C CNN
+	4    8900 5300
+	-1   0    0    -1  
+$EndComp
+Text GLabel 8950 1450 0    60   Input ~ 0
+GND
+Wire Wire Line
+	8600 1200 8950 1200
+Wire Wire Line
+	8950 1200 8950 1450
+Text GLabel 8950 2850 0    60   Input ~ 0
+GND
+Wire Wire Line
+	8600 2600 8950 2600
+Wire Wire Line
+	8950 2600 8950 2850
+Text GLabel 8950 4250 0    60   Input ~ 0
+GND
+Wire Wire Line
+	8600 4000 8950 4000
+Wire Wire Line
+	8950 4000 8950 4250
+Text GLabel 8950 5650 0    60   Input ~ 0
+GND
+Wire Wire Line
+	8600 5400 8950 5400
+Wire Wire Line
+	8950 5400 8950 5650
+$Comp
+L PORT U13
+U 17 1 6981AB9A
+P 4700 1300
+F 0 "U13" H 4750 1400 30  0000 C CNN
+F 1 "PORT" H 4700 1300 30  0000 C CNN
+F 2 "" H 4700 1300 60  0000 C CNN
+F 3 "" H 4700 1300 60  0000 C CNN
+	17   4700 1300
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 18 1 6981ABA0
+P 4700 2700
+F 0 "U13" H 4750 2800 30  0000 C CNN
+F 1 "PORT" H 4700 2700 30  0000 C CNN
+F 2 "" H 4700 2700 60  0000 C CNN
+F 3 "" H 4700 2700 60  0000 C CNN
+	18   4700 2700
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 19 1 6981ABA6
+P 4700 4100
+F 0 "U13" H 4750 4200 30  0000 C CNN
+F 1 "PORT" H 4700 4100 30  0000 C CNN
+F 2 "" H 4700 4100 60  0000 C CNN
+F 3 "" H 4700 4100 60  0000 C CNN
+	19   4700 4100
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 20 1 6981ABAC
+P 4700 5500
+F 0 "U13" H 4750 5600 30  0000 C CNN
+F 1 "PORT" H 4700 5500 30  0000 C CNN
+F 2 "" H 4700 5500 60  0000 C CNN
+F 3 "" H 4700 5500 60  0000 C CNN
+	20   4700 5500
+	-1   0    0    -1  
+$EndComp
+Text GLabel 4750 1650 0    60   Input ~ 0
+GND
+Wire Wire Line
+	4400 1400 4750 1400
+Wire Wire Line
+	4750 1400 4750 1650
+Text GLabel 4750 3050 0    60   Input ~ 0
+GND
+Wire Wire Line
+	4400 2800 4750 2800
+Wire Wire Line
+	4750 2800 4750 3050
+Text GLabel 4750 4450 0    60   Input ~ 0
+GND
+Wire Wire Line
+	4400 4200 4750 4200
+Wire Wire Line
+	4750 4200 4750 4450
+Text GLabel 4750 5850 0    60   Input ~ 0
+GND
+Wire Wire Line
+	4400 5600 4750 5600
+Wire Wire Line
+	4750 5600 4750 5850
+$Comp
+L PORT U13
+U 13 1 6981ADC6
+P 3800 1350
+F 0 "U13" H 3850 1450 30  0000 C CNN
+F 1 "PORT" H 3800 1350 30  0000 C CNN
+F 2 "" H 3800 1350 60  0000 C CNN
+F 3 "" H 3800 1350 60  0000 C CNN
+	13   3800 1350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 14 1 6981AEB1
+P 3800 2750
+F 0 "U13" H 3850 2850 30  0000 C CNN
+F 1 "PORT" H 3800 2750 30  0000 C CNN
+F 2 "" H 3800 2750 60  0000 C CNN
+F 3 "" H 3800 2750 60  0000 C CNN
+	14   3800 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 15 1 6981AF9C
+P 3800 4150
+F 0 "U13" H 3850 4250 30  0000 C CNN
+F 1 "PORT" H 3800 4150 30  0000 C CNN
+F 2 "" H 3800 4150 60  0000 C CNN
+F 3 "" H 3800 4150 60  0000 C CNN
+	15   3800 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 16 1 6981C7E6
+P 3800 5550
+F 0 "U13" H 3850 5650 30  0000 C CNN
+F 1 "PORT" H 3800 5550 30  0000 C CNN
+F 2 "" H 3800 5550 60  0000 C CNN
+F 3 "" H 3800 5550 60  0000 C CNN
+	16   3800 5550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 26 1 6981C8D1
+P 8000 5350
+F 0 "U13" H 8050 5450 30  0000 C CNN
+F 1 "PORT" H 8000 5350 30  0000 C CNN
+F 2 "" H 8000 5350 60  0000 C CNN
+F 3 "" H 8000 5350 60  0000 C CNN
+	26   8000 5350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 25 1 6981C9BE
+P 8000 3950
+F 0 "U13" H 8050 4050 30  0000 C CNN
+F 1 "PORT" H 8000 3950 30  0000 C CNN
+F 2 "" H 8000 3950 60  0000 C CNN
+F 3 "" H 8000 3950 60  0000 C CNN
+	25   8000 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 24 1 698216F3
+P 8000 2550
+F 0 "U13" H 8050 2650 30  0000 C CNN
+F 1 "PORT" H 8000 2550 30  0000 C CNN
+F 2 "" H 8000 2550 60  0000 C CNN
+F 3 "" H 8000 2550 60  0000 C CNN
+	24   8000 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 23 1 698217E2
+P 8000 1150
+F 0 "U13" H 8050 1250 30  0000 C CNN
+F 1 "PORT" H 8000 1150 30  0000 C CNN
+F 2 "" H 8000 1150 60  0000 C CNN
+F 3 "" H 8000 1150 60  0000 C CNN
+	23   8000 1150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U38
+U 5 1 698244A9
+P 12350 1300
+F 0 "U38" H 12400 1400 30  0000 C CNN
+F 1 "PORT" H 12350 1300 30  0000 C CNN
+F 2 "" H 12350 1300 60  0000 C CNN
+F 3 "" H 12350 1300 60  0000 C CNN
+	5    12350 1300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U38
+U 6 1 6982459E
+P 12350 2700
+F 0 "U38" H 12400 2800 30  0000 C CNN
+F 1 "PORT" H 12350 2700 30  0000 C CNN
+F 2 "" H 12350 2700 60  0000 C CNN
+F 3 "" H 12350 2700 60  0000 C CNN
+	6    12350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U38
+U 7 1 69824697
+P 12350 4100
+F 0 "U38" H 12400 4200 30  0000 C CNN
+F 1 "PORT" H 12350 4100 30  0000 C CNN
+F 2 "" H 12350 4100 60  0000 C CNN
+F 3 "" H 12350 4100 60  0000 C CNN
+	7    12350 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U38
+U 8 1 6982478E
+P 12350 5500
+F 0 "U38" H 12400 5600 30  0000 C CNN
+F 1 "PORT" H 12350 5500 30  0000 C CNN
+F 2 "" H 12350 5500 60  0000 C CNN
+F 3 "" H 12350 5500 60  0000 C CNN
+	8    12350 5500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 9 1 69825571
+P -50 200
+F 0 "U13" H 0   300 30  0000 C CNN
+F 1 "PORT" H -50 200 30  0000 C CNN
+F 2 "" H -50 200 60  0000 C CNN
+F 3 "" H -50 200 60  0000 C CNN
+	9    -50  200 
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 10 1 69825EB8
+P 1450 250
+F 0 "U13" H 1500 350 30  0000 C CNN
+F 1 "PORT" H 1450 250 30  0000 C CNN
+F 2 "" H 1450 250 60  0000 C CNN
+F 3 "" H 1450 250 60  0000 C CNN
+	10   1450 250 
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 11 1 69825FB7
+P 2550 250
+F 0 "U13" H 2600 350 30  0000 C CNN
+F 1 "PORT" H 2550 250 30  0000 C CNN
+F 2 "" H 2550 250 60  0000 C CNN
+F 3 "" H 2550 250 60  0000 C CNN
+	11   2550 250 
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 12 1 698260B6
+P 3800 250
+F 0 "U13" H 3850 350 30  0000 C CNN
+F 1 "PORT" H 3800 250 30  0000 C CNN
+F 2 "" H 3800 250 60  0000 C CNN
+F 3 "" H 3800 250 60  0000 C CNN
+	12   3800 250 
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U13
+U 21 1 698261B9
+P 4950 250
+F 0 "U13" H 5000 350 30  0000 C CNN
+F 1 "PORT" H 4950 250 30  0000 C CNN
+F 2 "" H 4950 250 60  0000 C CNN
+F 3 "" H 4950 250 60  0000 C CNN
+	21   4950 250 
+	1    0    0    -1  
+$EndComp
+Text GLabel 6450 250  2    60   Input ~ 0
+GND
+$Comp
+L PORT U13
+U 22 1 69826514
+P 6200 250
+F 0 "U13" H 6250 350 30  0000 C CNN
+F 1 "PORT" H 6200 250 30  0000 C CNN
+F 2 "" H 6200 250 60  0000 C CNN
+F 3 "" H 6200 250 60  0000 C CNN
+	22   6200 250 
+	1    0    0    -1  
+$EndComp
+Connection ~ -800 5700
+Connection ~ -800 2900
+Connection ~ -800 4300
+Connection ~ -800 1500
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/PI3B16244/PI3B16244.sub b/library/SubcircuitLibrary/PI3B16244/PI3B16244.sub
new file mode 100644
index 000000000..0731b9c77
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/PI3B16244.sub
@@ -0,0 +1,232 @@
+* Subcircuit PI3B16244
+.subckt PI3B16244 net-_m17-pad3_ net-_m18-pad3_ net-_m19-pad3_ net-_m20-pad3_ net-_m25-pad1_ net-_m26-pad1_ net-_m27-pad1_ net-_m28-pad1_ net-_m25-pad3_ net-_m26-pad3_ net-_m27-pad3_ net-_m28-pad3_ 
+* c:\fossee\esim\library\subcircuitlibrary\pi3b16244\pi3b16244.cir
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u1  1be_b net-_u1-pad2_ adc_bridge_1
+* u5  net-_u1-pad2_ net-_u5-pad2_ d_inverter
+m1 net-_m1-pad1_ 1be_b net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m5-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+* u9  net-_u5-pad2_ net-_m5-pad2_ dac_bridge_1
+* u2  1be_b net-_u2-pad2_ adc_bridge_1
+* u6  net-_u2-pad2_ net-_u10-pad1_ d_inverter
+m2 net-_m2-pad1_ 1be_b net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1
+m6 net-_m2-pad1_ net-_m6-pad2_ net-_m2-pad3_ vdd CMOSP W=100u L=100u M=1
+* u10  net-_u10-pad1_ net-_m6-pad2_ dac_bridge_1
+* u3  1be_b net-_u3-pad2_ adc_bridge_1
+* u7  net-_u3-pad2_ net-_u11-pad1_ d_inverter
+m3 net-_m3-pad1_ 1be_b net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1
+m7 net-_m3-pad1_ net-_m7-pad2_ net-_m3-pad3_ vdd CMOSP W=100u L=100u M=1
+* u11  net-_u11-pad1_ net-_m7-pad2_ dac_bridge_1
+* u4  1be_b net-_u4-pad2_ adc_bridge_1
+* u8  net-_u4-pad2_ net-_u12-pad1_ d_inverter
+m4 net-_m4-pad1_ 1be_b net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m4-pad1_ net-_m8-pad2_ net-_m4-pad3_ vdd CMOSP W=100u L=100u M=1
+* u12  net-_u12-pad1_ net-_m8-pad2_ dac_bridge_1
+* u26  3be_b net-_u26-pad2_ adc_bridge_1
+* u30  net-_u26-pad2_ net-_u30-pad2_ d_inverter
+m17 net-_m17-pad1_ 3be_b net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+m21 net-_m17-pad1_ net-_m21-pad2_ net-_m17-pad3_ vdd CMOSP W=100u L=100u M=1
+* u34  net-_u30-pad2_ net-_m21-pad2_ dac_bridge_1
+* u27  3be_b net-_u27-pad2_ adc_bridge_1
+* u31  net-_u27-pad2_ net-_u31-pad2_ d_inverter
+m18 net-_m18-pad1_ 3be_b net-_m18-pad3_ gnd CMOSN W=100u L=100u M=1
+m22 net-_m18-pad1_ net-_m22-pad2_ net-_m18-pad3_ vdd CMOSP W=100u L=100u M=1
+* u35  net-_u31-pad2_ net-_m22-pad2_ dac_bridge_1
+* u28  3be_b net-_u28-pad2_ adc_bridge_1
+* u32  net-_u28-pad2_ net-_u32-pad2_ d_inverter
+m19 net-_m19-pad1_ 3be_b net-_m19-pad3_ gnd CMOSN W=100u L=100u M=1
+m23 net-_m19-pad1_ net-_m23-pad2_ net-_m19-pad3_ vdd CMOSP W=100u L=100u M=1
+* u36  net-_u32-pad2_ net-_m23-pad2_ dac_bridge_1
+* u29  3be_b net-_u29-pad2_ adc_bridge_1
+* u33  net-_u29-pad2_ net-_u33-pad2_ d_inverter
+m20 net-_m20-pad1_ 3be_b net-_m20-pad3_ gnd CMOSN W=100u L=100u M=1
+m24 net-_m20-pad1_ net-_m24-pad2_ net-_m20-pad3_ vdd CMOSP W=100u L=100u M=1
+* u37  net-_u33-pad2_ net-_m24-pad2_ dac_bridge_1
+* u14  2be_b net-_u14-pad2_ adc_bridge_1
+* u18  net-_u14-pad2_ net-_u18-pad2_ d_inverter
+m9 net-_m13-pad1_ 2be_b net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m13-pad3_ vdd CMOSP W=100u L=100u M=1
+* u22  net-_u18-pad2_ net-_m13-pad2_ dac_bridge_1
+* u15  2be_b net-_u15-pad2_ adc_bridge_1
+* u19  net-_u15-pad2_ net-_u19-pad2_ d_inverter
+m10 net-_m10-pad1_ 2be_b net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1
+m14 net-_m10-pad1_ net-_m14-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+* u23  net-_u19-pad2_ net-_m14-pad2_ dac_bridge_1
+* u16  2be_b net-_u16-pad2_ adc_bridge_1
+* u20  net-_u16-pad2_ net-_u20-pad2_ d_inverter
+m11 net-_m11-pad1_ 2be_b net-_m11-pad3_ gnd CMOSN W=100u L=100u M=1
+m15 net-_m11-pad1_ net-_m15-pad2_ net-_m11-pad3_ vdd CMOSP W=100u L=100u M=1
+* u24  net-_u20-pad2_ net-_m15-pad2_ dac_bridge_1
+* u17  2be_b net-_u17-pad2_ adc_bridge_1
+* u21  net-_u17-pad2_ net-_u21-pad2_ d_inverter
+m12 net-_m12-pad1_ 2be_b net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m16 net-_m12-pad1_ net-_m16-pad2_ net-_m12-pad3_ vdd CMOSP W=100u L=100u M=1
+* u25  net-_u21-pad2_ net-_m16-pad2_ dac_bridge_1
+* u39  4be_b net-_u39-pad2_ adc_bridge_1
+* u44  net-_u39-pad2_ net-_u44-pad2_ d_inverter
+m25 net-_m25-pad1_ 4be_b net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m29 net-_m25-pad1_ net-_m29-pad2_ net-_m25-pad3_ vdd CMOSP W=100u L=100u M=1
+* u48  net-_u44-pad2_ net-_m29-pad2_ dac_bridge_1
+* u40  4be_b net-_u40-pad2_ adc_bridge_1
+* u45  net-_u40-pad2_ net-_u45-pad2_ d_inverter
+m26 net-_m26-pad1_ 4be_b net-_m26-pad3_ gnd CMOSN W=100u L=100u M=1
+m30 net-_m26-pad1_ net-_m30-pad2_ net-_m26-pad3_ vdd CMOSP W=100u L=100u M=1
+* u49  net-_u45-pad2_ net-_m30-pad2_ dac_bridge_1
+* u41  4be_b net-_u41-pad2_ adc_bridge_1
+* u46  net-_u41-pad2_ net-_u46-pad2_ d_inverter
+m27 net-_m27-pad1_ 4be_b net-_m27-pad3_ gnd CMOSN W=100u L=100u M=1
+m31 net-_m27-pad1_ net-_m31-pad2_ net-_m27-pad3_ vdd CMOSP W=100u L=100u M=1
+* u50  net-_u46-pad2_ net-_m31-pad2_ dac_bridge_1
+* u42  4be_b net-_u42-pad2_ adc_bridge_1
+* u47  net-_u42-pad2_ net-_u47-pad2_ d_inverter
+m28 net-_m28-pad1_ 4be_b net-_m28-pad3_ gnd CMOSN W=100u L=100u M=1
+m32 net-_m28-pad1_ net-_m32-pad2_ net-_m28-pad3_ vdd CMOSP W=100u L=100u M=1
+* u51  net-_u47-pad2_ net-_m32-pad2_ dac_bridge_1
+a1 [1be_b ] [net-_u1-pad2_ ] u1
+a2 net-_u1-pad2_ net-_u5-pad2_ u5
+a3 [net-_u5-pad2_ ] [net-_m5-pad2_ ] u9
+a4 [1be_b ] [net-_u2-pad2_ ] u2
+a5 net-_u2-pad2_ net-_u10-pad1_ u6
+a6 [net-_u10-pad1_ ] [net-_m6-pad2_ ] u10
+a7 [1be_b ] [net-_u3-pad2_ ] u3
+a8 net-_u3-pad2_ net-_u11-pad1_ u7
+a9 [net-_u11-pad1_ ] [net-_m7-pad2_ ] u11
+a10 [1be_b ] [net-_u4-pad2_ ] u4
+a11 net-_u4-pad2_ net-_u12-pad1_ u8
+a12 [net-_u12-pad1_ ] [net-_m8-pad2_ ] u12
+a13 [3be_b ] [net-_u26-pad2_ ] u26
+a14 net-_u26-pad2_ net-_u30-pad2_ u30
+a15 [net-_u30-pad2_ ] [net-_m21-pad2_ ] u34
+a16 [3be_b ] [net-_u27-pad2_ ] u27
+a17 net-_u27-pad2_ net-_u31-pad2_ u31
+a18 [net-_u31-pad2_ ] [net-_m22-pad2_ ] u35
+a19 [3be_b ] [net-_u28-pad2_ ] u28
+a20 net-_u28-pad2_ net-_u32-pad2_ u32
+a21 [net-_u32-pad2_ ] [net-_m23-pad2_ ] u36
+a22 [3be_b ] [net-_u29-pad2_ ] u29
+a23 net-_u29-pad2_ net-_u33-pad2_ u33
+a24 [net-_u33-pad2_ ] [net-_m24-pad2_ ] u37
+a25 [2be_b ] [net-_u14-pad2_ ] u14
+a26 net-_u14-pad2_ net-_u18-pad2_ u18
+a27 [net-_u18-pad2_ ] [net-_m13-pad2_ ] u22
+a28 [2be_b ] [net-_u15-pad2_ ] u15
+a29 net-_u15-pad2_ net-_u19-pad2_ u19
+a30 [net-_u19-pad2_ ] [net-_m14-pad2_ ] u23
+a31 [2be_b ] [net-_u16-pad2_ ] u16
+a32 net-_u16-pad2_ net-_u20-pad2_ u20
+a33 [net-_u20-pad2_ ] [net-_m15-pad2_ ] u24
+a34 [2be_b ] [net-_u17-pad2_ ] u17
+a35 net-_u17-pad2_ net-_u21-pad2_ u21
+a36 [net-_u21-pad2_ ] [net-_m16-pad2_ ] u25
+a37 [4be_b ] [net-_u39-pad2_ ] u39
+a38 net-_u39-pad2_ net-_u44-pad2_ u44
+a39 [net-_u44-pad2_ ] [net-_m29-pad2_ ] u48
+a40 [4be_b ] [net-_u40-pad2_ ] u40
+a41 net-_u40-pad2_ net-_u45-pad2_ u45
+a42 [net-_u45-pad2_ ] [net-_m30-pad2_ ] u49
+a43 [4be_b ] [net-_u41-pad2_ ] u41
+a44 net-_u41-pad2_ net-_u46-pad2_ u46
+a45 [net-_u46-pad2_ ] [net-_m31-pad2_ ] u50
+a46 [4be_b ] [net-_u42-pad2_ ] u42
+a47 net-_u42-pad2_ net-_u47-pad2_ u47
+a48 [net-_u47-pad2_ ] [net-_m32-pad2_ ] u51
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u26 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u27 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u28 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u36 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u29 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u37 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u39 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u48 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u40 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u49 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u41 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u50 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u42 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u51 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends PI3B16244
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/PI3B16244/PI3B16244_Previous_Values.xml b/library/SubcircuitLibrary/PI3B16244/PI3B16244_Previous_Values.xml
new file mode 100644
index 000000000..8364ad572
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/PI3B16244_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u5 name="type">d_inverter<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /></u5><u9 name="type">dac_bridge<field8 name="Enter value for out_low (default=0.0)" /><field9 name="Enter value for out_high (default=5.0)" /><field10 name="Enter value for out_undef (default=0.5)" /><field11 name="Enter value for input load (default=1.0e-12)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /></u9><u2 name="type">adc_bridge<field14 name="Enter value for in_low (default=1.0)" /><field15 name="Enter value for in_high (default=2.0)" /><field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /></u2><u6 name="type">d_inverter<field18 name="Enter Rise Delay (default=1.0e-9)" /><field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /></u6><u10 name="type">dac_bridge<field21 name="Enter value for out_low (default=0.0)" /><field22 name="Enter value for out_high (default=5.0)" /><field23 name="Enter value for out_undef (default=0.5)" /><field24 name="Enter value for input load (default=1.0e-12)" /><field25 name="Enter the Rise Time (default=1.0e-9)" /><field26 name="Enter the Fall Time (default=1.0e-9)" /></u10><u3 name="type">adc_bridge<field27 name="Enter value for in_low (default=1.0)" /><field28 name="Enter value for in_high (default=2.0)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u3><u7 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u7><u11 name="type">dac_bridge<field34 name="Enter value for out_low (default=0.0)" /><field35 name="Enter value for out_high (default=5.0)" /><field36 name="Enter value for out_undef (default=0.5)" /><field37 name="Enter value for input load (default=1.0e-12)" /><field38 name="Enter the Rise Time (default=1.0e-9)" /><field39 name="Enter the Fall Time (default=1.0e-9)" /></u11><u4 name="type">adc_bridge<field40 name="Enter value for in_low (default=1.0)" /><field41 name="Enter value for in_high (default=2.0)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /><field43 name="Enter Fall Delay (default=1.0e-9)" /></u4><u8 name="type">d_inverter<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u8><u12 name="type">dac_bridge<field47 name="Enter value for out_low (default=0.0)" /><field48 name="Enter value for out_high (default=5.0)" /><field49 name="Enter value for out_undef (default=0.5)" /><field50 name="Enter value for input load (default=1.0e-12)" /><field51 name="Enter the Rise Time (default=1.0e-9)" /><field52 name="Enter the Fall Time (default=1.0e-9)" /></u12><u26 name="type">adc_bridge<field53 name="Enter value for in_low (default=1.0)" /><field54 name="Enter value for in_high (default=2.0)" /><field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /></u26><u30 name="type">d_inverter<field57 name="Enter Rise Delay (default=1.0e-9)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /></u30><u34 name="type">dac_bridge<field60 name="Enter value for out_low (default=0.0)" /><field61 name="Enter value for out_high (default=5.0)" /><field62 name="Enter value for out_undef (default=0.5)" /><field63 name="Enter value for input load (default=1.0e-12)" /><field64 name="Enter the Rise Time (default=1.0e-9)" /><field65 name="Enter the Fall Time (default=1.0e-9)" /></u34><u27 name="type">adc_bridge<field66 name="Enter value for in_low (default=1.0)" /><field67 name="Enter value for in_high (default=2.0)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /></u27><u31 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u31><u35 name="type">dac_bridge<field73 name="Enter value for out_low (default=0.0)" /><field74 name="Enter value for out_high (default=5.0)" /><field75 name="Enter value for out_undef (default=0.5)" /><field76 name="Enter value for input load (default=1.0e-12)" /><field77 name="Enter the Rise Time (default=1.0e-9)" /><field78 name="Enter the Fall Time (default=1.0e-9)" /></u35><u28 name="type">adc_bridge<field79 name="Enter value for in_low (default=1.0)" /><field80 name="Enter value for in_high (default=2.0)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /><field82 name="Enter Fall Delay (default=1.0e-9)" /></u28><u32 name="type">d_inverter<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u32><u36 name="type">dac_bridge<field86 name="Enter value for out_low (default=0.0)" /><field87 name="Enter value for out_high (default=5.0)" /><field88 name="Enter value for out_undef (default=0.5)" /><field89 name="Enter value for input load (default=1.0e-12)" /><field90 name="Enter the Rise Time (default=1.0e-9)" /><field91 name="Enter the Fall Time (default=1.0e-9)" /></u36><u29 name="type">adc_bridge<field92 name="Enter value for in_low (default=1.0)" /><field93 name="Enter value for in_high (default=2.0)" /><field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /></u29><u33 name="type">d_inverter<field96 name="Enter Rise Delay (default=1.0e-9)" /><field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /></u33><u37 name="type">dac_bridge<field99 name="Enter value for out_low (default=0.0)" /><field100 name="Enter value for out_high (default=5.0)" /><field101 name="Enter value for out_undef (default=0.5)" /><field102 name="Enter value for input load (default=1.0e-12)" /><field103 name="Enter the Rise Time (default=1.0e-9)" /><field104 name="Enter the Fall Time (default=1.0e-9)" /></u37><u14 name="type">adc_bridge<field105 name="Enter value for in_low (default=1.0)" /><field106 name="Enter value for in_high (default=2.0)" /><field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /></u14><u18 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u18><u22 name="type">dac_bridge<field112 name="Enter value for out_low (default=0.0)" /><field113 name="Enter value for out_high (default=5.0)" /><field114 name="Enter value for out_undef (default=0.5)" /><field115 name="Enter value for input load (default=1.0e-12)" /><field116 name="Enter the Rise Time (default=1.0e-9)" /><field117 name="Enter the Fall Time (default=1.0e-9)" /></u22><u15 name="type">adc_bridge<field118 name="Enter value for in_low (default=1.0)" /><field119 name="Enter value for in_high (default=2.0)" /><field120 name="Enter Rise Delay (default=1.0e-9)" /><field121 name="Enter Fall Delay (default=1.0e-9)" /></u15><u19 name="type">d_inverter<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u19><u23 name="type">dac_bridge<field125 name="Enter value for out_low (default=0.0)" /><field126 name="Enter value for out_high (default=5.0)" /><field127 name="Enter value for out_undef (default=0.5)" /><field128 name="Enter value for input load (default=1.0e-12)" /><field129 name="Enter the Rise Time (default=1.0e-9)" /><field130 name="Enter the Fall Time (default=1.0e-9)" /></u23><u16 name="type">adc_bridge<field131 name="Enter value for in_low (default=1.0)" /><field132 name="Enter value for in_high (default=2.0)" /><field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /></u16><u20 name="type">d_inverter<field135 name="Enter Rise Delay (default=1.0e-9)" /><field136 name="Enter Fall Delay (default=1.0e-9)" /><field137 name="Enter Input Load (default=1.0e-12)" /></u20><u24 name="type">dac_bridge<field138 name="Enter value for out_low (default=0.0)" /><field139 name="Enter value for out_high (default=5.0)" /><field140 name="Enter value for out_undef (default=0.5)" /><field141 name="Enter value for input load (default=1.0e-12)" /><field142 name="Enter the Rise Time (default=1.0e-9)" /><field143 name="Enter the Fall Time (default=1.0e-9)" /></u24><u17 name="type">adc_bridge<field144 name="Enter value for in_low (default=1.0)" /><field145 name="Enter value for in_high (default=2.0)" /><field146 name="Enter Rise Delay (default=1.0e-9)" /><field147 name="Enter Fall Delay (default=1.0e-9)" /></u17><u21 name="type">d_inverter<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u21><u25 name="type">dac_bridge<field151 name="Enter value for out_low (default=0.0)" /><field152 name="Enter value for out_high (default=5.0)" /><field153 name="Enter value for out_undef (default=0.5)" /><field154 name="Enter value for input load (default=1.0e-12)" /><field155 name="Enter the Rise Time (default=1.0e-9)" /><field156 name="Enter the Fall Time (default=1.0e-9)" /></u25><u39 name="type">adc_bridge<field157 name="Enter value for in_low (default=1.0)" /><field158 name="Enter value for in_high (default=2.0)" /><field159 name="Enter Rise Delay (default=1.0e-9)" /><field160 name="Enter Fall Delay (default=1.0e-9)" /></u39><u44 name="type">d_inverter<field161 name="Enter Rise Delay (default=1.0e-9)" /><field162 name="Enter Fall Delay (default=1.0e-9)" /><field163 name="Enter Input Load (default=1.0e-12)" /></u44><u48 name="type">dac_bridge<field164 name="Enter value for out_low (default=0.0)" /><field165 name="Enter value for out_high (default=5.0)" /><field166 name="Enter value for out_undef (default=0.5)" /><field167 name="Enter value for input load (default=1.0e-12)" /><field168 name="Enter the Rise Time (default=1.0e-9)" /><field169 name="Enter the Fall Time (default=1.0e-9)" /></u48><u40 name="type">adc_bridge<field170 name="Enter value for in_low (default=1.0)" /><field171 name="Enter value for in_high (default=2.0)" /><field172 name="Enter Rise Delay (default=1.0e-9)" /><field173 name="Enter Fall Delay (default=1.0e-9)" /></u40><u45 name="type">d_inverter<field174 name="Enter Rise Delay (default=1.0e-9)" /><field175 name="Enter Fall Delay (default=1.0e-9)" /><field176 name="Enter Input Load (default=1.0e-12)" /></u45><u49 name="type">dac_bridge<field177 name="Enter value for out_low (default=0.0)" /><field178 name="Enter value for out_high (default=5.0)" /><field179 name="Enter value for out_undef (default=0.5)" /><field180 name="Enter value for input load (default=1.0e-12)" /><field181 name="Enter the Rise Time (default=1.0e-9)" /><field182 name="Enter the Fall Time (default=1.0e-9)" /></u49><u41 name="type">adc_bridge<field183 name="Enter value for in_low (default=1.0)" /><field184 name="Enter value for in_high (default=2.0)" /><field185 name="Enter Rise Delay (default=1.0e-9)" /><field186 name="Enter Fall Delay (default=1.0e-9)" /></u41><u46 name="type">d_inverter<field187 name="Enter Rise Delay (default=1.0e-9)" /><field188 name="Enter Fall Delay (default=1.0e-9)" /><field189 name="Enter Input Load (default=1.0e-12)" /></u46><u50 name="type">dac_bridge<field190 name="Enter value for out_low (default=0.0)" /><field191 name="Enter value for out_high (default=5.0)" /><field192 name="Enter value for out_undef (default=0.5)" /><field193 name="Enter value for input load (default=1.0e-12)" /><field194 name="Enter the Rise Time (default=1.0e-9)" /><field195 name="Enter the Fall Time (default=1.0e-9)" /></u50><u42 name="type">adc_bridge<field196 name="Enter value for in_low (default=1.0)" /><field197 name="Enter value for in_high (default=2.0)" /><field198 name="Enter Rise Delay (default=1.0e-9)" /><field199 name="Enter Fall Delay (default=1.0e-9)" /></u42><u47 name="type">d_inverter<field200 name="Enter Rise Delay (default=1.0e-9)" /><field201 name="Enter Fall Delay (default=1.0e-9)" /><field202 name="Enter Input Load (default=1.0e-12)" /></u47><u51 name="type">dac_bridge<field203 name="Enter value for out_low (default=0.0)" /><field204 name="Enter value for out_high (default=5.0)" /><field205 name="Enter value for out_undef (default=0.5)" /><field206 name="Enter value for input load (default=1.0e-12)" /><field207 name="Enter the Rise Time (default=1.0e-9)" /><field208 name="Enter the Fall Time (default=1.0e-9)" /></u51></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m5><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m7><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m8><m17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m17><m21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m21><m18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m18><m22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m22><m19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m19><m23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m23><m20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m20><m24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m24><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m9><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m13><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m10><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m14><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m11><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m15><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m12><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m16><m25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m25><m29><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m29><m26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m26><m30><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m30><m27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m27><m31><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m31><m28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m28><m32><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m32></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/PI3B16244/PMOS-180nm.lib b/library/SubcircuitLibrary/PI3B16244/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/PI3B16244/analysis b/library/SubcircuitLibrary/PI3B16244/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B16244/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/PI3B3384/NMOS-180nm.lib b/library/SubcircuitLibrary/PI3B3384/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/PI3B3384/PI3B3384-cache.lib b/library/SubcircuitLibrary/PI3B3384/PI3B3384-cache.lib
new file mode 100644
index 000000000..a55745972
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/PI3B3384-cache.lib
@@ -0,0 +1,142 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/PI3B3384/PI3B3384.cir b/library/SubcircuitLibrary/PI3B3384/PI3B3384.cir
new file mode 100644
index 000000000..583394500
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/PI3B3384.cir
@@ -0,0 +1,61 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\PI3B3384\PI3B3384.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/30/26 20:25:28
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  BEA_B Net-_U1-Pad2_ adc_bridge_1		
+U6  Net-_U1-Pad2_ Net-_U11-Pad1_ d_inverter		
+M1  Net-_M1-Pad1_ BEA_B Net-_M1-Pad3_ GND eSim_MOS_N		
+M6  Net-_M1-Pad1_ Net-_M6-Pad2_ Net-_M1-Pad3_ VDD eSim_MOS_P		
+U11  Net-_U11-Pad1_ Net-_M6-Pad2_ dac_bridge_1		
+U2  BEA_B Net-_U2-Pad2_ adc_bridge_1		
+U7  Net-_U2-Pad2_ Net-_U12-Pad1_ d_inverter		
+M2  Net-_M2-Pad1_ BEA_B Net-_M2-Pad3_ GND eSim_MOS_N		
+M7  Net-_M2-Pad1_ Net-_M7-Pad2_ Net-_M2-Pad3_ VDD eSim_MOS_P		
+U12  Net-_U12-Pad1_ Net-_M7-Pad2_ dac_bridge_1		
+U3  BEA_B Net-_U3-Pad2_ adc_bridge_1		
+U8  Net-_U3-Pad2_ Net-_U13-Pad1_ d_inverter		
+M3  Net-_M3-Pad1_ BEA_B Net-_M3-Pad3_ GND eSim_MOS_N		
+M8  Net-_M3-Pad1_ Net-_M8-Pad2_ Net-_M3-Pad3_ VDD eSim_MOS_P		
+U13  Net-_U13-Pad1_ Net-_M8-Pad2_ dac_bridge_1		
+U4  BEA_B Net-_U4-Pad2_ adc_bridge_1		
+U9  Net-_U4-Pad2_ Net-_U14-Pad1_ d_inverter		
+M4  Net-_M4-Pad1_ BEA_B Net-_M4-Pad3_ GND eSim_MOS_N		
+M9  Net-_M4-Pad1_ Net-_M9-Pad2_ Net-_M4-Pad3_ VDD eSim_MOS_P		
+U14  Net-_U14-Pad1_ Net-_M9-Pad2_ dac_bridge_1		
+U17  BEB_B Net-_U17-Pad2_ adc_bridge_1		
+U22  Net-_U17-Pad2_ Net-_U22-Pad2_ d_inverter		
+M11  Net-_M11-Pad1_ BEB_B Net-_M11-Pad3_ GND eSim_MOS_N		
+M16  Net-_M11-Pad1_ Net-_M16-Pad2_ Net-_M11-Pad3_ VDD eSim_MOS_P		
+U27  Net-_U22-Pad2_ Net-_M16-Pad2_ dac_bridge_1		
+U18  BEB_B Net-_U18-Pad2_ adc_bridge_1		
+U23  Net-_U18-Pad2_ Net-_U23-Pad2_ d_inverter		
+M12  Net-_M12-Pad1_ BEB_B Net-_M12-Pad3_ GND eSim_MOS_N		
+M17  Net-_M12-Pad1_ Net-_M17-Pad2_ Net-_M12-Pad3_ VDD eSim_MOS_P		
+U28  Net-_U23-Pad2_ Net-_M17-Pad2_ dac_bridge_1		
+U19  BEB_B Net-_U19-Pad2_ adc_bridge_1		
+U24  Net-_U19-Pad2_ Net-_U24-Pad2_ d_inverter		
+M13  Net-_M13-Pad1_ BEB_B Net-_M13-Pad3_ GND eSim_MOS_N		
+M18  Net-_M13-Pad1_ Net-_M18-Pad2_ Net-_M13-Pad3_ VDD eSim_MOS_P		
+U29  Net-_U24-Pad2_ Net-_M18-Pad2_ dac_bridge_1		
+U20  BEB_B Net-_U20-Pad2_ adc_bridge_1		
+U25  Net-_U20-Pad2_ Net-_U25-Pad2_ d_inverter		
+M14  Net-_M14-Pad1_ BEB_B Net-_M14-Pad3_ GND eSim_MOS_N		
+M19  Net-_M14-Pad1_ Net-_M19-Pad2_ Net-_M14-Pad3_ VDD eSim_MOS_P		
+U30  Net-_U25-Pad2_ Net-_M19-Pad2_ dac_bridge_1		
+U5  BEA_B Net-_U10-Pad1_ adc_bridge_1		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter		
+M5  Net-_M10-Pad1_ BEA_B Net-_M10-Pad3_ GND eSim_MOS_N		
+M10  Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ VDD eSim_MOS_P		
+U15  Net-_U10-Pad2_ Net-_M10-Pad2_ dac_bridge_1		
+U21  BEB_B Net-_U21-Pad2_ adc_bridge_1		
+U26  Net-_U21-Pad2_ Net-_U26-Pad2_ d_inverter		
+M15  Net-_M15-Pad1_ BEB_B Net-_M15-Pad3_ GND eSim_MOS_N		
+M20  Net-_M15-Pad1_ Net-_M20-Pad2_ Net-_M15-Pad3_ VDD eSim_MOS_P		
+U31  Net-_U26-Pad2_ Net-_M20-Pad2_ dac_bridge_1		
+U16  Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M3-Pad1_ Net-_M4-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad3_ Net-_M2-Pad3_ Net-_M3-Pad3_ Net-_M4-Pad3_ Net-_M10-Pad3_ Net-_M11-Pad1_ Net-_M12-Pad1_ Net-_M13-Pad1_ Net-_M14-Pad1_ Net-_M15-Pad1_ Net-_M11-Pad3_ Net-_M12-Pad3_ Net-_M13-Pad3_ Net-_M14-Pad3_ Net-_M15-Pad3_ BEB_B BEA_B VDD GND PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/PI3B3384/PI3B3384.cir.out b/library/SubcircuitLibrary/PI3B3384/PI3B3384.cir.out
new file mode 100644
index 000000000..6452ba76f
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/PI3B3384.cir.out
@@ -0,0 +1,154 @@
+* c:\fossee\esim\library\subcircuitlibrary\pi3b3384\pi3b3384.cir
+
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u1  bea_b net-_u1-pad2_ adc_bridge_1
+* u6  net-_u1-pad2_ net-_u11-pad1_ d_inverter
+m1 net-_m1-pad1_ bea_b net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m6-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+* u11  net-_u11-pad1_ net-_m6-pad2_ dac_bridge_1
+* u2  bea_b net-_u2-pad2_ adc_bridge_1
+* u7  net-_u2-pad2_ net-_u12-pad1_ d_inverter
+m2 net-_m2-pad1_ bea_b net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1
+m7 net-_m2-pad1_ net-_m7-pad2_ net-_m2-pad3_ vdd CMOSP W=100u L=100u M=1
+* u12  net-_u12-pad1_ net-_m7-pad2_ dac_bridge_1
+* u3  bea_b net-_u3-pad2_ adc_bridge_1
+* u8  net-_u3-pad2_ net-_u13-pad1_ d_inverter
+m3 net-_m3-pad1_ bea_b net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m3-pad1_ net-_m8-pad2_ net-_m3-pad3_ vdd CMOSP W=100u L=100u M=1
+* u13  net-_u13-pad1_ net-_m8-pad2_ dac_bridge_1
+* u4  bea_b net-_u4-pad2_ adc_bridge_1
+* u9  net-_u4-pad2_ net-_u14-pad1_ d_inverter
+m4 net-_m4-pad1_ bea_b net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1
+m9 net-_m4-pad1_ net-_m9-pad2_ net-_m4-pad3_ vdd CMOSP W=100u L=100u M=1
+* u14  net-_u14-pad1_ net-_m9-pad2_ dac_bridge_1
+* u17  beb_b net-_u17-pad2_ adc_bridge_1
+* u22  net-_u17-pad2_ net-_u22-pad2_ d_inverter
+m11 net-_m11-pad1_ beb_b net-_m11-pad3_ gnd CMOSN W=100u L=100u M=1
+m16 net-_m11-pad1_ net-_m16-pad2_ net-_m11-pad3_ vdd CMOSP W=100u L=100u M=1
+* u27  net-_u22-pad2_ net-_m16-pad2_ dac_bridge_1
+* u18  beb_b net-_u18-pad2_ adc_bridge_1
+* u23  net-_u18-pad2_ net-_u23-pad2_ d_inverter
+m12 net-_m12-pad1_ beb_b net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m17 net-_m12-pad1_ net-_m17-pad2_ net-_m12-pad3_ vdd CMOSP W=100u L=100u M=1
+* u28  net-_u23-pad2_ net-_m17-pad2_ dac_bridge_1
+* u19  beb_b net-_u19-pad2_ adc_bridge_1
+* u24  net-_u19-pad2_ net-_u24-pad2_ d_inverter
+m13 net-_m13-pad1_ beb_b net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m18 net-_m13-pad1_ net-_m18-pad2_ net-_m13-pad3_ vdd CMOSP W=100u L=100u M=1
+* u29  net-_u24-pad2_ net-_m18-pad2_ dac_bridge_1
+* u20  beb_b net-_u20-pad2_ adc_bridge_1
+* u25  net-_u20-pad2_ net-_u25-pad2_ d_inverter
+m14 net-_m14-pad1_ beb_b net-_m14-pad3_ gnd CMOSN W=100u L=100u M=1
+m19 net-_m14-pad1_ net-_m19-pad2_ net-_m14-pad3_ vdd CMOSP W=100u L=100u M=1
+* u30  net-_u25-pad2_ net-_m19-pad2_ dac_bridge_1
+* u5  bea_b net-_u10-pad1_ adc_bridge_1
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+m5 net-_m10-pad1_ bea_b net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+* u15  net-_u10-pad2_ net-_m10-pad2_ dac_bridge_1
+* u21  beb_b net-_u21-pad2_ adc_bridge_1
+* u26  net-_u21-pad2_ net-_u26-pad2_ d_inverter
+m15 net-_m15-pad1_ beb_b net-_m15-pad3_ gnd CMOSN W=100u L=100u M=1
+m20 net-_m15-pad1_ net-_m20-pad2_ net-_m15-pad3_ vdd CMOSP W=100u L=100u M=1
+* u31  net-_u26-pad2_ net-_m20-pad2_ dac_bridge_1
+* u16  net-_m1-pad1_ net-_m2-pad1_ net-_m3-pad1_ net-_m4-pad1_ net-_m10-pad1_ net-_m1-pad3_ net-_m2-pad3_ net-_m3-pad3_ net-_m4-pad3_ net-_m10-pad3_ net-_m11-pad1_ net-_m12-pad1_ net-_m13-pad1_ net-_m14-pad1_ net-_m15-pad1_ net-_m11-pad3_ net-_m12-pad3_ net-_m13-pad3_ net-_m14-pad3_ net-_m15-pad3_ beb_b bea_b vdd gnd port
+a1 [bea_b ] [net-_u1-pad2_ ] u1
+a2 net-_u1-pad2_ net-_u11-pad1_ u6
+a3 [net-_u11-pad1_ ] [net-_m6-pad2_ ] u11
+a4 [bea_b ] [net-_u2-pad2_ ] u2
+a5 net-_u2-pad2_ net-_u12-pad1_ u7
+a6 [net-_u12-pad1_ ] [net-_m7-pad2_ ] u12
+a7 [bea_b ] [net-_u3-pad2_ ] u3
+a8 net-_u3-pad2_ net-_u13-pad1_ u8
+a9 [net-_u13-pad1_ ] [net-_m8-pad2_ ] u13
+a10 [bea_b ] [net-_u4-pad2_ ] u4
+a11 net-_u4-pad2_ net-_u14-pad1_ u9
+a12 [net-_u14-pad1_ ] [net-_m9-pad2_ ] u14
+a13 [beb_b ] [net-_u17-pad2_ ] u17
+a14 net-_u17-pad2_ net-_u22-pad2_ u22
+a15 [net-_u22-pad2_ ] [net-_m16-pad2_ ] u27
+a16 [beb_b ] [net-_u18-pad2_ ] u18
+a17 net-_u18-pad2_ net-_u23-pad2_ u23
+a18 [net-_u23-pad2_ ] [net-_m17-pad2_ ] u28
+a19 [beb_b ] [net-_u19-pad2_ ] u19
+a20 net-_u19-pad2_ net-_u24-pad2_ u24
+a21 [net-_u24-pad2_ ] [net-_m18-pad2_ ] u29
+a22 [beb_b ] [net-_u20-pad2_ ] u20
+a23 net-_u20-pad2_ net-_u25-pad2_ u25
+a24 [net-_u25-pad2_ ] [net-_m19-pad2_ ] u30
+a25 [bea_b ] [net-_u10-pad1_ ] u5
+a26 net-_u10-pad1_ net-_u10-pad2_ u10
+a27 [net-_u10-pad2_ ] [net-_m10-pad2_ ] u15
+a28 [beb_b ] [net-_u21-pad2_ ] u21
+a29 net-_u21-pad2_ net-_u26-pad2_ u26
+a30 [net-_u26-pad2_ ] [net-_m20-pad2_ ] u31
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u18 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u19 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u20 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u21 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/PI3B3384/PI3B3384.pro b/library/SubcircuitLibrary/PI3B3384/PI3B3384.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/PI3B3384.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/PI3B3384/PI3B3384.sch b/library/SubcircuitLibrary/PI3B3384/PI3B3384.sch
new file mode 100644
index 000000000..a28c34f2b
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/PI3B3384.sch
@@ -0,0 +1,1149 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:PI3B3384-cache
+EELAYER 25 0
+EELAYER END
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+U 1 1 697CC6DC
+P 5750 3500
+F 0 "U19" H 5750 3500 60  0000 C CNN
+F 1 "adc_bridge_1" H 5750 3650 60  0000 C CNN
+F 2 "" H 5750 3500 60  0000 C CNN
+F 3 "" H 5750 3500 60  0000 C CNN
+	1    5750 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U24
+U 1 1 697CC6DD
+P 6650 3450
+F 0 "U24" H 6650 3350 60  0000 C CNN
+F 1 "d_inverter" H 6650 3600 60  0000 C CNN
+F 2 "" H 6700 3400 60  0000 C CNN
+F 3 "" H 6700 3400 60  0000 C CNN
+	1    6650 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M13
+U 1 1 697CC6DE
+P 8250 4300
+F 0 "M13" H 8250 4150 50  0000 R CNN
+F 1 "eSim_MOS_N" H 8350 4250 50  0000 R CNN
+F 2 "" H 8550 4000 29  0000 C CNN
+F 3 "" H 8350 4100 60  0000 C CNN
+	1    8250 4300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M18
+U 1 1 697CC6DF
+P 8450 3600
+F 0 "M18" H 8400 3650 50  0000 R CNN
+F 1 "eSim_MOS_P" H 8500 3750 50  0000 R CNN
+F 2 "" H 8700 3700 29  0000 C CNN
+F 3 "" H 8500 3600 60  0000 C CNN
+	1    8450 3600
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	8250 3750 8250 4100
+Wire Wire Line
+	8650 3750 8650 4100
+Wire Wire Line
+	6350 3450 6300 3450
+Connection ~ 8250 3950
+$Comp
+L dac_bridge_1 U29
+U 1 1 697CC6E0
+P 7550 3500
+F 0 "U29" H 7550 3500 60  0000 C CNN
+F 1 "dac_bridge_1" H 7550 3650 60  0000 C CNN
+F 2 "" H 7550 3500 60  0000 C CNN
+F 3 "" H 7550 3500 60  0000 C CNN
+	1    7550 3500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8100 3450 8450 3450
+Wire Wire Line
+	8450 4400 5150 4400
+Connection ~ 5150 4400
+Connection ~ 8650 3900
+Text GLabel 8600 3850 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	5150 4400 5150 3450
+Text GLabel 5150 5800 0    60   Input ~ 0
+BEB_B
+$Comp
+L adc_bridge_1 U20
+U 1 1 697CC6E3
+P 5750 4900
+F 0 "U20" H 5750 4900 60  0000 C CNN
+F 1 "adc_bridge_1" H 5750 5050 60  0000 C CNN
+F 2 "" H 5750 4900 60  0000 C CNN
+F 3 "" H 5750 4900 60  0000 C CNN
+	1    5750 4900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U25
+U 1 1 697CC6E4
+P 6650 4850
+F 0 "U25" H 6650 4750 60  0000 C CNN
+F 1 "d_inverter" H 6650 5000 60  0000 C CNN
+F 2 "" H 6700 4800 60  0000 C CNN
+F 3 "" H 6700 4800 60  0000 C CNN
+	1    6650 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M14
+U 1 1 697CC6E5
+P 8250 5700
+F 0 "M14" H 8250 5550 50  0000 R CNN
+F 1 "eSim_MOS_N" H 8350 5650 50  0000 R CNN
+F 2 "" H 8550 5400 29  0000 C CNN
+F 3 "" H 8350 5500 60  0000 C CNN
+	1    8250 5700
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M19
+U 1 1 697CC6E6
+P 8450 5000
+F 0 "M19" H 8400 5050 50  0000 R CNN
+F 1 "eSim_MOS_P" H 8500 5150 50  0000 R CNN
+F 2 "" H 8700 5100 29  0000 C CNN
+F 3 "" H 8500 5000 60  0000 C CNN
+	1    8450 5000
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	8250 5150 8250 5500
+Wire Wire Line
+	8650 5150 8650 5500
+Wire Wire Line
+	6350 4850 6300 4850
+Connection ~ 8250 5350
+$Comp
+L dac_bridge_1 U30
+U 1 1 697CC6E7
+P 7550 4900
+F 0 "U30" H 7550 4900 60  0000 C CNN
+F 1 "dac_bridge_1" H 7550 5050 60  0000 C CNN
+F 2 "" H 7550 4900 60  0000 C CNN
+F 3 "" H 7550 4900 60  0000 C CNN
+	1    7550 4900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8100 4850 8450 4850
+Wire Wire Line
+	8450 5800 5150 5800
+Connection ~ 5150 5800
+Connection ~ 8650 5300
+Text GLabel 8600 5250 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	5150 5800 5150 4850
+Text GLabel 850  7250 0    60   Input ~ 0
+BEA_B
+$Comp
+L adc_bridge_1 U5
+U 1 1 697CC6EA
+P 1450 6350
+F 0 "U5" H 1450 6350 60  0000 C CNN
+F 1 "adc_bridge_1" H 1450 6500 60  0000 C CNN
+F 2 "" H 1450 6350 60  0000 C CNN
+F 3 "" H 1450 6350 60  0000 C CNN
+	1    1450 6350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 697CC6EB
+P 2350 6300
+F 0 "U10" H 2350 6200 60  0000 C CNN
+F 1 "d_inverter" H 2350 6450 60  0000 C CNN
+F 2 "" H 2400 6250 60  0000 C CNN
+F 3 "" H 2400 6250 60  0000 C CNN
+	1    2350 6300
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 697CC6EC
+P 3950 7150
+F 0 "M5" H 3950 7000 50  0000 R CNN
+F 1 "eSim_MOS_N" H 4050 7100 50  0000 R CNN
+F 2 "" H 4250 6850 29  0000 C CNN
+F 3 "" H 4050 6950 60  0000 C CNN
+	1    3950 7150
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M10
+U 1 1 697CC6ED
+P 4150 6450
+F 0 "M10" H 4100 6500 50  0000 R CNN
+F 1 "eSim_MOS_P" H 4200 6600 50  0000 R CNN
+F 2 "" H 4400 6550 29  0000 C CNN
+F 3 "" H 4200 6450 60  0000 C CNN
+	1    4150 6450
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	3950 6600 3950 6950
+Wire Wire Line
+	4350 6600 4350 6950
+Wire Wire Line
+	2050 6300 2000 6300
+Connection ~ 3950 6800
+$Comp
+L dac_bridge_1 U15
+U 1 1 697CC6EE
+P 3250 6350
+F 0 "U15" H 3250 6350 60  0000 C CNN
+F 1 "dac_bridge_1" H 3250 6500 60  0000 C CNN
+F 2 "" H 3250 6350 60  0000 C CNN
+F 3 "" H 3250 6350 60  0000 C CNN
+	1    3250 6350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3800 6300 4150 6300
+Wire Wire Line
+	4150 7250 850  7250
+Connection ~ 850  7250
+Connection ~ 4350 6750
+Text GLabel 4300 6700 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	850  7250 850  6300
+Text GLabel 5200 7050 0    60   Input ~ 0
+BEB_B
+$Comp
+L adc_bridge_1 U21
+U 1 1 697CC6F1
+P 5800 6150
+F 0 "U21" H 5800 6150 60  0000 C CNN
+F 1 "adc_bridge_1" H 5800 6300 60  0000 C CNN
+F 2 "" H 5800 6150 60  0000 C CNN
+F 3 "" H 5800 6150 60  0000 C CNN
+	1    5800 6150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U26
+U 1 1 697CC6F2
+P 6700 6100
+F 0 "U26" H 6700 6000 60  0000 C CNN
+F 1 "d_inverter" H 6700 6250 60  0000 C CNN
+F 2 "" H 6750 6050 60  0000 C CNN
+F 3 "" H 6750 6050 60  0000 C CNN
+	1    6700 6100
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M15
+U 1 1 697CC6F3
+P 8300 6950
+F 0 "M15" H 8300 6800 50  0000 R CNN
+F 1 "eSim_MOS_N" H 8400 6900 50  0000 R CNN
+F 2 "" H 8600 6650 29  0000 C CNN
+F 3 "" H 8400 6750 60  0000 C CNN
+	1    8300 6950
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_MOS_P M20
+U 1 1 697CC6F4
+P 8500 6250
+F 0 "M20" H 8450 6300 50  0000 R CNN
+F 1 "eSim_MOS_P" H 8550 6400 50  0000 R CNN
+F 2 "" H 8750 6350 29  0000 C CNN
+F 3 "" H 8550 6250 60  0000 C CNN
+	1    8500 6250
+	0    -1   1    0   
+$EndComp
+Wire Wire Line
+	8300 6400 8300 6750
+Wire Wire Line
+	8700 6400 8700 6750
+Wire Wire Line
+	6400 6100 6350 6100
+Connection ~ 8300 6600
+$Comp
+L dac_bridge_1 U31
+U 1 1 697CC6F5
+P 7600 6150
+F 0 "U31" H 7600 6150 60  0000 C CNN
+F 1 "dac_bridge_1" H 7600 6300 60  0000 C CNN
+F 2 "" H 7600 6150 60  0000 C CNN
+F 3 "" H 7600 6150 60  0000 C CNN
+	1    7600 6150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8150 6100 8500 6100
+Wire Wire Line
+	8500 7050 5200 7050
+Connection ~ 5200 7050
+Connection ~ 8700 6550
+Text GLabel 8650 6500 0    60   Input ~ 0
+VDD
+Wire Wire Line
+	5200 7050 5200 6100
+Wire Wire Line
+	4350 1200 4450 1200
+Wire Wire Line
+	4350 2600 4450 2600
+Wire Wire Line
+	4350 4000 4450 4000
+Wire Wire Line
+	4350 5400 4450 5400
+$Comp
+L PORT U16
+U 6 1 697D2C09
+P 4700 1200
+F 0 "U16" H 4750 1300 30  0000 C CNN
+F 1 "PORT" H 4700 1200 30  0000 C CNN
+F 2 "" H 4700 1200 60  0000 C CNN
+F 3 "" H 4700 1200 60  0000 C CNN
+	6    4700 1200
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 1 1 697D2CD4
+P 3700 1250
+F 0 "U16" H 3750 1350 30  0000 C CNN
+F 1 "PORT" H 3700 1250 30  0000 C CNN
+F 2 "" H 3700 1250 60  0000 C CNN
+F 3 "" H 3700 1250 60  0000 C CNN
+	1    3700 1250
+	1    0    0    -1  
+$EndComp
+Text GLabel 4500 1400 2    60   Input ~ 0
+GND
+Wire Wire Line
+	4300 1300 4500 1300
+Wire Wire Line
+	4500 1300 4500 1400
+$Comp
+L PORT U16
+U 7 1 697D46DC
+P 4700 2600
+F 0 "U16" H 4750 2700 30  0000 C CNN
+F 1 "PORT" H 4700 2600 30  0000 C CNN
+F 2 "" H 4700 2600 60  0000 C CNN
+F 3 "" H 4700 2600 60  0000 C CNN
+	7    4700 2600
+	-1   0    0    -1  
+$EndComp
+Text GLabel 4500 2800 2    60   Input ~ 0
+GND
+Wire Wire Line
+	4300 2700 4500 2700
+Wire Wire Line
+	4500 2700 4500 2800
+$Comp
+L PORT U16
+U 8 1 697D56D8
+P 4700 4000
+F 0 "U16" H 4750 4100 30  0000 C CNN
+F 1 "PORT" H 4700 4000 30  0000 C CNN
+F 2 "" H 4700 4000 60  0000 C CNN
+F 3 "" H 4700 4000 60  0000 C CNN
+	8    4700 4000
+	-1   0    0    -1  
+$EndComp
+Text GLabel 4500 4200 2    60   Input ~ 0
+GND
+Wire Wire Line
+	4300 4100 4500 4100
+Wire Wire Line
+	4500 4100 4500 4200
+$Comp
+L PORT U16
+U 2 1 697D575B
+P 3700 2650
+F 0 "U16" H 3750 2750 30  0000 C CNN
+F 1 "PORT" H 3700 2650 30  0000 C CNN
+F 2 "" H 3700 2650 60  0000 C CNN
+F 3 "" H 3700 2650 60  0000 C CNN
+	2    3700 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 9 1 697D67D0
+P 4700 5400
+F 0 "U16" H 4750 5500 30  0000 C CNN
+F 1 "PORT" H 4700 5400 30  0000 C CNN
+F 2 "" H 4700 5400 60  0000 C CNN
+F 3 "" H 4700 5400 60  0000 C CNN
+	9    4700 5400
+	-1   0    0    -1  
+$EndComp
+Text GLabel 4500 5600 2    60   Input ~ 0
+GND
+Wire Wire Line
+	4300 5500 4500 5500
+Wire Wire Line
+	4500 5500 4500 5600
+$Comp
+L PORT U16
+U 3 1 697D6894
+P 3700 4050
+F 0 "U16" H 3750 4150 30  0000 C CNN
+F 1 "PORT" H 3700 4050 30  0000 C CNN
+F 2 "" H 3700 4050 60  0000 C CNN
+F 3 "" H 3700 4050 60  0000 C CNN
+	3    3700 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 4 1 697D6927
+P 3700 5450
+F 0 "U16" H 3750 5550 30  0000 C CNN
+F 1 "PORT" H 3700 5450 30  0000 C CNN
+F 2 "" H 3700 5450 60  0000 C CNN
+F 3 "" H 3700 5450 60  0000 C CNN
+	4    3700 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 5 1 697D811D
+P 3700 6800
+F 0 "U16" H 3750 6900 30  0000 C CNN
+F 1 "PORT" H 3700 6800 30  0000 C CNN
+F 2 "" H 3700 6800 60  0000 C CNN
+F 3 "" H 3700 6800 60  0000 C CNN
+	5    3700 6800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 10 1 697D8891
+P 4700 6750
+F 0 "U16" H 4750 6850 30  0000 C CNN
+F 1 "PORT" H 4700 6750 30  0000 C CNN
+F 2 "" H 4700 6750 60  0000 C CNN
+F 3 "" H 4700 6750 60  0000 C CNN
+	10   4700 6750
+	-1   0    0    -1  
+$EndComp
+Text GLabel 4500 6950 2    60   Input ~ 0
+GND
+Wire Wire Line
+	4300 6850 4500 6850
+Wire Wire Line
+	4500 6850 4500 6950
+Wire Wire Line
+	4350 6750 4450 6750
+Wire Wire Line
+	8650 2500 8750 2500
+Wire Wire Line
+	8650 3900 8750 3900
+Wire Wire Line
+	8650 5300 8750 5300
+$Comp
+L PORT U16
+U 17 1 697DE4D1
+P 9000 2500
+F 0 "U16" H 9050 2600 30  0000 C CNN
+F 1 "PORT" H 9000 2500 30  0000 C CNN
+F 2 "" H 9000 2500 60  0000 C CNN
+F 3 "" H 9000 2500 60  0000 C CNN
+	17   9000 2500
+	-1   0    0    -1  
+$EndComp
+Text GLabel 8800 2700 2    60   Input ~ 0
+GND
+Wire Wire Line
+	8600 2600 8800 2600
+Wire Wire Line
+	8800 2600 8800 2700
+$Comp
+L PORT U16
+U 18 1 697DE4DA
+P 9000 3900
+F 0 "U16" H 9050 4000 30  0000 C CNN
+F 1 "PORT" H 9000 3900 30  0000 C CNN
+F 2 "" H 9000 3900 60  0000 C CNN
+F 3 "" H 9000 3900 60  0000 C CNN
+	18   9000 3900
+	-1   0    0    -1  
+$EndComp
+Text GLabel 8800 4100 2    60   Input ~ 0
+GND
+Wire Wire Line
+	8600 4000 8800 4000
+Wire Wire Line
+	8800 4000 8800 4100
+$Comp
+L PORT U16
+U 19 1 697DE4E3
+P 9000 5300
+F 0 "U16" H 9050 5400 30  0000 C CNN
+F 1 "PORT" H 9000 5300 30  0000 C CNN
+F 2 "" H 9000 5300 60  0000 C CNN
+F 3 "" H 9000 5300 60  0000 C CNN
+	19   9000 5300
+	-1   0    0    -1  
+$EndComp
+Text GLabel 8800 5500 2    60   Input ~ 0
+GND
+Wire Wire Line
+	8600 5400 8800 5400
+Wire Wire Line
+	8800 5400 8800 5500
+$Comp
+L PORT U16
+U 20 1 697DE4EC
+P 9050 6550
+F 0 "U16" H 9100 6650 30  0000 C CNN
+F 1 "PORT" H 9050 6550 30  0000 C CNN
+F 2 "" H 9050 6550 60  0000 C CNN
+F 3 "" H 9050 6550 60  0000 C CNN
+	20   9050 6550
+	-1   0    0    -1  
+$EndComp
+Text GLabel 8850 6750 2    60   Input ~ 0
+GND
+Wire Wire Line
+	8650 6650 8850 6650
+Wire Wire Line
+	8850 6650 8850 6750
+Wire Wire Line
+	8700 6550 8800 6550
+Wire Wire Line
+	8650 1100 8750 1100
+$Comp
+L PORT U16
+U 16 1 697E4B47
+P 9000 1100
+F 0 "U16" H 9050 1200 30  0000 C CNN
+F 1 "PORT" H 9000 1100 30  0000 C CNN
+F 2 "" H 9000 1100 60  0000 C CNN
+F 3 "" H 9000 1100 60  0000 C CNN
+	16   9000 1100
+	-1   0    0    -1  
+$EndComp
+Text GLabel 8800 1300 2    60   Input ~ 0
+GND
+Wire Wire Line
+	8600 1200 8800 1200
+Wire Wire Line
+	8800 1200 8800 1300
+Text GLabel 10400 1150 2    60   Input ~ 0
+BEA_B
+Text GLabel 10350 1650 2    60   Input ~ 0
+BEB_B
+$Comp
+L PORT U16
+U 15 1 697EBACD
+P 8050 6600
+F 0 "U16" H 8100 6700 30  0000 C CNN
+F 1 "PORT" H 8050 6600 30  0000 C CNN
+F 2 "" H 8050 6600 60  0000 C CNN
+F 3 "" H 8050 6600 60  0000 C CNN
+	15   8050 6600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 14 1 697EBB68
+P 8000 5350
+F 0 "U16" H 8050 5450 30  0000 C CNN
+F 1 "PORT" H 8000 5350 30  0000 C CNN
+F 2 "" H 8000 5350 60  0000 C CNN
+F 3 "" H 8000 5350 60  0000 C CNN
+	14   8000 5350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 13 1 697EBC03
+P 8000 3950
+F 0 "U16" H 8050 4050 30  0000 C CNN
+F 1 "PORT" H 8000 3950 30  0000 C CNN
+F 2 "" H 8000 3950 60  0000 C CNN
+F 3 "" H 8000 3950 60  0000 C CNN
+	13   8000 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 12 1 697EDD4C
+P 8000 2550
+F 0 "U16" H 8050 2650 30  0000 C CNN
+F 1 "PORT" H 8000 2550 30  0000 C CNN
+F 2 "" H 8000 2550 60  0000 C CNN
+F 3 "" H 8000 2550 60  0000 C CNN
+	12   8000 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 11 1 697EDDED
+P 8000 1150
+F 0 "U16" H 8050 1250 30  0000 C CNN
+F 1 "PORT" H 8000 1150 30  0000 C CNN
+F 2 "" H 8000 1150 60  0000 C CNN
+F 3 "" H 8000 1150 60  0000 C CNN
+	11   8000 1150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 22 1 697EDE8E
+P 10150 1150
+F 0 "U16" H 10200 1250 30  0000 C CNN
+F 1 "PORT" H 10150 1150 30  0000 C CNN
+F 2 "" H 10150 1150 60  0000 C CNN
+F 3 "" H 10150 1150 60  0000 C CNN
+	22   10150 1150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 21 1 697EDF35
+P 10100 1650
+F 0 "U16" H 10150 1750 30  0000 C CNN
+F 1 "PORT" H 10100 1650 30  0000 C CNN
+F 2 "" H 10100 1650 60  0000 C CNN
+F 3 "" H 10100 1650 60  0000 C CNN
+	21   10100 1650
+	1    0    0    -1  
+$EndComp
+Text GLabel 10450 1950 2    60   Input ~ 0
+VDD
+Text GLabel 10450 2250 2    60   Input ~ 0
+GND
+$Comp
+L PORT U16
+U 23 1 697EE226
+P 10200 1950
+F 0 "U16" H 10250 2050 30  0000 C CNN
+F 1 "PORT" H 10200 1950 30  0000 C CNN
+F 2 "" H 10200 1950 60  0000 C CNN
+F 3 "" H 10200 1950 60  0000 C CNN
+	23   10200 1950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U16
+U 24 1 697EE2CF
+P 10200 2250
+F 0 "U16" H 10250 2350 30  0000 C CNN
+F 1 "PORT" H 10200 2250 30  0000 C CNN
+F 2 "" H 10200 2250 60  0000 C CNN
+F 3 "" H 10200 2250 60  0000 C CNN
+	24   10200 2250
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/PI3B3384/PI3B3384.sub b/library/SubcircuitLibrary/PI3B3384/PI3B3384.sub
new file mode 100644
index 000000000..e3dff84f4
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/PI3B3384.sub
@@ -0,0 +1,148 @@
+* Subcircuit PI3B3384
+.subckt PI3B3384 net-_m1-pad1_ net-_m2-pad1_ net-_m3-pad1_ net-_m4-pad1_ net-_m10-pad1_ net-_m1-pad3_ net-_m2-pad3_ net-_m3-pad3_ net-_m4-pad3_ net-_m10-pad3_ net-_m11-pad1_ net-_m12-pad1_ net-_m13-pad1_ net-_m14-pad1_ net-_m15-pad1_ net-_m11-pad3_ net-_m12-pad3_ net-_m13-pad3_ net-_m14-pad3_ net-_m15-pad3_ beb_b bea_b vdd gnd 
+* c:\fossee\esim\library\subcircuitlibrary\pi3b3384\pi3b3384.cir
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u1  bea_b net-_u1-pad2_ adc_bridge_1
+* u6  net-_u1-pad2_ net-_u11-pad1_ d_inverter
+m1 net-_m1-pad1_ bea_b net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m6-pad2_ net-_m1-pad3_ vdd CMOSP W=100u L=100u M=1
+* u11  net-_u11-pad1_ net-_m6-pad2_ dac_bridge_1
+* u2  bea_b net-_u2-pad2_ adc_bridge_1
+* u7  net-_u2-pad2_ net-_u12-pad1_ d_inverter
+m2 net-_m2-pad1_ bea_b net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1
+m7 net-_m2-pad1_ net-_m7-pad2_ net-_m2-pad3_ vdd CMOSP W=100u L=100u M=1
+* u12  net-_u12-pad1_ net-_m7-pad2_ dac_bridge_1
+* u3  bea_b net-_u3-pad2_ adc_bridge_1
+* u8  net-_u3-pad2_ net-_u13-pad1_ d_inverter
+m3 net-_m3-pad1_ bea_b net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m3-pad1_ net-_m8-pad2_ net-_m3-pad3_ vdd CMOSP W=100u L=100u M=1
+* u13  net-_u13-pad1_ net-_m8-pad2_ dac_bridge_1
+* u4  bea_b net-_u4-pad2_ adc_bridge_1
+* u9  net-_u4-pad2_ net-_u14-pad1_ d_inverter
+m4 net-_m4-pad1_ bea_b net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1
+m9 net-_m4-pad1_ net-_m9-pad2_ net-_m4-pad3_ vdd CMOSP W=100u L=100u M=1
+* u14  net-_u14-pad1_ net-_m9-pad2_ dac_bridge_1
+* u17  beb_b net-_u17-pad2_ adc_bridge_1
+* u22  net-_u17-pad2_ net-_u22-pad2_ d_inverter
+m11 net-_m11-pad1_ beb_b net-_m11-pad3_ gnd CMOSN W=100u L=100u M=1
+m16 net-_m11-pad1_ net-_m16-pad2_ net-_m11-pad3_ vdd CMOSP W=100u L=100u M=1
+* u27  net-_u22-pad2_ net-_m16-pad2_ dac_bridge_1
+* u18  beb_b net-_u18-pad2_ adc_bridge_1
+* u23  net-_u18-pad2_ net-_u23-pad2_ d_inverter
+m12 net-_m12-pad1_ beb_b net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m17 net-_m12-pad1_ net-_m17-pad2_ net-_m12-pad3_ vdd CMOSP W=100u L=100u M=1
+* u28  net-_u23-pad2_ net-_m17-pad2_ dac_bridge_1
+* u19  beb_b net-_u19-pad2_ adc_bridge_1
+* u24  net-_u19-pad2_ net-_u24-pad2_ d_inverter
+m13 net-_m13-pad1_ beb_b net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m18 net-_m13-pad1_ net-_m18-pad2_ net-_m13-pad3_ vdd CMOSP W=100u L=100u M=1
+* u29  net-_u24-pad2_ net-_m18-pad2_ dac_bridge_1
+* u20  beb_b net-_u20-pad2_ adc_bridge_1
+* u25  net-_u20-pad2_ net-_u25-pad2_ d_inverter
+m14 net-_m14-pad1_ beb_b net-_m14-pad3_ gnd CMOSN W=100u L=100u M=1
+m19 net-_m14-pad1_ net-_m19-pad2_ net-_m14-pad3_ vdd CMOSP W=100u L=100u M=1
+* u30  net-_u25-pad2_ net-_m19-pad2_ dac_bridge_1
+* u5  bea_b net-_u10-pad1_ adc_bridge_1
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+m5 net-_m10-pad1_ bea_b net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+* u15  net-_u10-pad2_ net-_m10-pad2_ dac_bridge_1
+* u21  beb_b net-_u21-pad2_ adc_bridge_1
+* u26  net-_u21-pad2_ net-_u26-pad2_ d_inverter
+m15 net-_m15-pad1_ beb_b net-_m15-pad3_ gnd CMOSN W=100u L=100u M=1
+m20 net-_m15-pad1_ net-_m20-pad2_ net-_m15-pad3_ vdd CMOSP W=100u L=100u M=1
+* u31  net-_u26-pad2_ net-_m20-pad2_ dac_bridge_1
+a1 [bea_b ] [net-_u1-pad2_ ] u1
+a2 net-_u1-pad2_ net-_u11-pad1_ u6
+a3 [net-_u11-pad1_ ] [net-_m6-pad2_ ] u11
+a4 [bea_b ] [net-_u2-pad2_ ] u2
+a5 net-_u2-pad2_ net-_u12-pad1_ u7
+a6 [net-_u12-pad1_ ] [net-_m7-pad2_ ] u12
+a7 [bea_b ] [net-_u3-pad2_ ] u3
+a8 net-_u3-pad2_ net-_u13-pad1_ u8
+a9 [net-_u13-pad1_ ] [net-_m8-pad2_ ] u13
+a10 [bea_b ] [net-_u4-pad2_ ] u4
+a11 net-_u4-pad2_ net-_u14-pad1_ u9
+a12 [net-_u14-pad1_ ] [net-_m9-pad2_ ] u14
+a13 [beb_b ] [net-_u17-pad2_ ] u17
+a14 net-_u17-pad2_ net-_u22-pad2_ u22
+a15 [net-_u22-pad2_ ] [net-_m16-pad2_ ] u27
+a16 [beb_b ] [net-_u18-pad2_ ] u18
+a17 net-_u18-pad2_ net-_u23-pad2_ u23
+a18 [net-_u23-pad2_ ] [net-_m17-pad2_ ] u28
+a19 [beb_b ] [net-_u19-pad2_ ] u19
+a20 net-_u19-pad2_ net-_u24-pad2_ u24
+a21 [net-_u24-pad2_ ] [net-_m18-pad2_ ] u29
+a22 [beb_b ] [net-_u20-pad2_ ] u20
+a23 net-_u20-pad2_ net-_u25-pad2_ u25
+a24 [net-_u25-pad2_ ] [net-_m19-pad2_ ] u30
+a25 [bea_b ] [net-_u10-pad1_ ] u5
+a26 net-_u10-pad1_ net-_u10-pad2_ u10
+a27 [net-_u10-pad2_ ] [net-_m10-pad2_ ] u15
+a28 [beb_b ] [net-_u21-pad2_ ] u21
+a29 net-_u21-pad2_ net-_u26-pad2_ u26
+a30 [net-_u26-pad2_ ] [net-_m20-pad2_ ] u31
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u18 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u19 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u20 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u21 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends PI3B3384
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/PI3B3384/PI3B3384_Previous_Values.xml b/library/SubcircuitLibrary/PI3B3384/PI3B3384_Previous_Values.xml
new file mode 100644
index 000000000..008d49bd7
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/PI3B3384_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u6 name="type">d_inverter<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /></u6><u11 name="type">dac_bridge<field8 name="Enter value for out_low (default=0.0)" /><field9 name="Enter value for out_high (default=5.0)" /><field10 name="Enter value for out_undef (default=0.5)" /><field11 name="Enter value for input load (default=1.0e-12)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /></u11><u2 name="type">adc_bridge<field14 name="Enter value for in_low (default=1.0)" /><field15 name="Enter value for in_high (default=2.0)" /><field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /></u2><u7 name="type">d_inverter<field18 name="Enter Rise Delay (default=1.0e-9)" /><field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /></u7><u12 name="type">dac_bridge<field21 name="Enter value for out_low (default=0.0)" /><field22 name="Enter value for out_high (default=5.0)" /><field23 name="Enter value for out_undef (default=0.5)" /><field24 name="Enter value for input load (default=1.0e-12)" /><field25 name="Enter the Rise Time (default=1.0e-9)" /><field26 name="Enter the Fall Time (default=1.0e-9)" /></u12><u3 name="type">adc_bridge<field27 name="Enter value for in_low (default=1.0)" /><field28 name="Enter value for in_high (default=2.0)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u3><u8 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u8><u13 name="type">dac_bridge<field34 name="Enter value for out_low (default=0.0)" /><field35 name="Enter value for out_high (default=5.0)" /><field36 name="Enter value for out_undef (default=0.5)" /><field37 name="Enter value for input load (default=1.0e-12)" /><field38 name="Enter the Rise Time (default=1.0e-9)" /><field39 name="Enter the Fall Time (default=1.0e-9)" /></u13><u4 name="type">adc_bridge<field40 name="Enter value for in_low (default=1.0)" /><field41 name="Enter value for in_high (default=2.0)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /><field43 name="Enter Fall Delay (default=1.0e-9)" /></u4><u9 name="type">d_inverter<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u9><u14 name="type">dac_bridge<field47 name="Enter value for out_low (default=0.0)" /><field48 name="Enter value for out_high (default=5.0)" /><field49 name="Enter value for out_undef (default=0.5)" /><field50 name="Enter value for input load (default=1.0e-12)" /><field51 name="Enter the Rise Time (default=1.0e-9)" /><field52 name="Enter the Fall Time (default=1.0e-9)" /></u14><u17 name="type">adc_bridge<field53 name="Enter value for in_low (default=1.0)" /><field54 name="Enter value for in_high (default=2.0)" /><field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /></u17><u22 name="type">d_inverter<field57 name="Enter Rise Delay (default=1.0e-9)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /></u22><u27 name="type">dac_bridge<field60 name="Enter value for out_low (default=0.0)" /><field61 name="Enter value for out_high (default=5.0)" /><field62 name="Enter value for out_undef (default=0.5)" /><field63 name="Enter value for input load (default=1.0e-12)" /><field64 name="Enter the Rise Time (default=1.0e-9)" /><field65 name="Enter the Fall Time (default=1.0e-9)" /></u27><u18 name="type">adc_bridge<field66 name="Enter value for in_low (default=1.0)" /><field67 name="Enter value for in_high (default=2.0)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /></u18><u23 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u23><u28 name="type">dac_bridge<field73 name="Enter value for out_low (default=0.0)" /><field74 name="Enter value for out_high (default=5.0)" /><field75 name="Enter value for out_undef (default=0.5)" /><field76 name="Enter value for input load (default=1.0e-12)" /><field77 name="Enter the Rise Time (default=1.0e-9)" /><field78 name="Enter the Fall Time (default=1.0e-9)" /></u28><u19 name="type">adc_bridge<field79 name="Enter value for in_low (default=1.0)" /><field80 name="Enter value for in_high (default=2.0)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /><field82 name="Enter Fall Delay (default=1.0e-9)" /></u19><u24 name="type">d_inverter<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u24><u29 name="type">dac_bridge<field86 name="Enter value for out_low (default=0.0)" /><field87 name="Enter value for out_high (default=5.0)" /><field88 name="Enter value for out_undef (default=0.5)" /><field89 name="Enter value for input load (default=1.0e-12)" /><field90 name="Enter the Rise Time (default=1.0e-9)" /><field91 name="Enter the Fall Time (default=1.0e-9)" /></u29><u20 name="type">adc_bridge<field92 name="Enter value for in_low (default=1.0)" /><field93 name="Enter value for in_high (default=2.0)" /><field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /></u20><u25 name="type">d_inverter<field96 name="Enter Rise Delay (default=1.0e-9)" /><field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /></u25><u30 name="type">dac_bridge<field99 name="Enter value for out_low (default=0.0)" /><field100 name="Enter value for out_high (default=5.0)" /><field101 name="Enter value for out_undef (default=0.5)" /><field102 name="Enter value for input load (default=1.0e-12)" /><field103 name="Enter the Rise Time (default=1.0e-9)" /><field104 name="Enter the Fall Time (default=1.0e-9)" /></u30><u5 name="type">adc_bridge<field105 name="Enter value for in_low (default=1.0)" /><field106 name="Enter value for in_high (default=2.0)" /><field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /></u5><u10 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u10><u15 name="type">dac_bridge<field112 name="Enter value for out_low (default=0.0)" /><field113 name="Enter value for out_high (default=5.0)" /><field114 name="Enter value for out_undef (default=0.5)" /><field115 name="Enter value for input load (default=1.0e-12)" /><field116 name="Enter the Rise Time (default=1.0e-9)" /><field117 name="Enter the Fall Time (default=1.0e-9)" /></u15><u21 name="type">adc_bridge<field118 name="Enter value for in_low (default=1.0)" /><field119 name="Enter value for in_high (default=2.0)" /><field120 name="Enter Rise Delay (default=1.0e-9)" /><field121 name="Enter Fall Delay (default=1.0e-9)" /></u21><u26 name="type">d_inverter<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u26><u31 name="type">dac_bridge<field125 name="Enter value for out_low (default=0.0)" /><field126 name="Enter value for out_high (default=5.0)" /><field127 name="Enter value for out_undef (default=0.5)" /><field128 name="Enter value for input load (default=1.0e-12)" /><field129 name="Enter the Rise Time (default=1.0e-9)" /><field130 name="Enter the Fall Time (default=1.0e-9)" /></u31></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m7><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m8><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m9><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m11><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m16><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m12><m17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m17><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m13><m18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m18><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m14><m19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m19><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m10><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m15><m20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m20></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/PI3B3384/PMOS-180nm.lib b/library/SubcircuitLibrary/PI3B3384/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/PI3B3384/analysis b/library/SubcircuitLibrary/PI3B3384/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/PI3B3384/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/NMOS-180nm.lib b/library/SubcircuitLibrary/SN74LVC3G17/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/PMOS-180nm.lib b/library/SubcircuitLibrary/SN74LVC3G17/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17-cache.lib b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17-cache.lib
new file mode 100644
index 000000000..6c512720e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.cir b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.cir
new file mode 100644
index 000000000..892621f74
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.cir
@@ -0,0 +1,47 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LVC3G17\SN74LVC3G17.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/30/26 14:28:54
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M4  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad1_ VDD eSim_MOS_P		
+M3  Net-_M3-Pad1_ Net-_M1-Pad2_ VDD VDD eSim_MOS_P		
+M9  GND Net-_M1-Pad1_ Net-_M3-Pad1_ VDD eSim_MOS_P		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND eSim_MOS_N		
+M2  Net-_M1-Pad3_ Net-_M1-Pad2_ GND GND eSim_MOS_N		
+M11  VDD Net-_M1-Pad1_ Net-_M1-Pad3_ GND eSim_MOS_N		
+M16  Net-_M13-Pad1_ Net-_M1-Pad1_ Net-_M15-Pad1_ VDD eSim_MOS_P		
+M15  Net-_M15-Pad1_ Net-_M1-Pad1_ VDD VDD eSim_MOS_P		
+M21  GND Net-_M13-Pad1_ Net-_M15-Pad1_ VDD eSim_MOS_P		
+M13  Net-_M13-Pad1_ Net-_M1-Pad1_ Net-_M13-Pad3_ GND eSim_MOS_N		
+M14  Net-_M13-Pad3_ Net-_M1-Pad1_ GND GND eSim_MOS_N		
+M23  VDD Net-_M13-Pad1_ Net-_M13-Pad3_ GND eSim_MOS_N		
+M8  Net-_M10-Pad2_ Net-_M5-Pad2_ Net-_M10-Pad3_ VDD eSim_MOS_P		
+M7  Net-_M10-Pad3_ Net-_M5-Pad2_ VDD VDD eSim_MOS_P		
+M10  GND Net-_M10-Pad2_ Net-_M10-Pad3_ VDD eSim_MOS_P		
+M5  Net-_M10-Pad2_ Net-_M5-Pad2_ Net-_M12-Pad3_ GND eSim_MOS_N		
+M6  Net-_M12-Pad3_ Net-_M5-Pad2_ GND GND eSim_MOS_N		
+M12  VDD Net-_M10-Pad2_ Net-_M12-Pad3_ GND eSim_MOS_N		
+M20  Net-_M17-Pad1_ Net-_M10-Pad2_ Net-_M19-Pad1_ VDD eSim_MOS_P		
+M19  Net-_M19-Pad1_ Net-_M10-Pad2_ VDD VDD eSim_MOS_P		
+M22  GND Net-_M17-Pad1_ Net-_M19-Pad1_ VDD eSim_MOS_P		
+M17  Net-_M17-Pad1_ Net-_M10-Pad2_ Net-_M17-Pad3_ GND eSim_MOS_N		
+M18  Net-_M17-Pad3_ Net-_M10-Pad2_ GND GND eSim_MOS_N		
+M24  VDD Net-_M17-Pad1_ Net-_M17-Pad3_ GND eSim_MOS_N		
+M28  Net-_M25-Pad1_ Net-_M25-Pad2_ Net-_M27-Pad1_ VDD eSim_MOS_P		
+M27  Net-_M27-Pad1_ Net-_M25-Pad2_ VDD VDD eSim_MOS_P		
+M29  GND Net-_M25-Pad1_ Net-_M27-Pad1_ VDD eSim_MOS_P		
+M25  Net-_M25-Pad1_ Net-_M25-Pad2_ Net-_M25-Pad3_ GND eSim_MOS_N		
+M26  Net-_M25-Pad3_ Net-_M25-Pad2_ GND GND eSim_MOS_N		
+M30  VDD Net-_M25-Pad1_ Net-_M25-Pad3_ GND eSim_MOS_N		
+M34  Net-_M31-Pad1_ Net-_M25-Pad1_ Net-_M33-Pad1_ VDD eSim_MOS_P		
+M33  Net-_M33-Pad1_ Net-_M25-Pad1_ VDD VDD eSim_MOS_P		
+M35  GND Net-_M31-Pad1_ Net-_M33-Pad1_ VDD eSim_MOS_P		
+M31  Net-_M31-Pad1_ Net-_M25-Pad1_ Net-_M31-Pad3_ GND eSim_MOS_N		
+M32  Net-_M31-Pad3_ Net-_M25-Pad1_ GND GND eSim_MOS_N		
+M36  VDD Net-_M31-Pad1_ Net-_M31-Pad3_ GND eSim_MOS_N		
+U1  Net-_M1-Pad2_ Net-_M5-Pad2_ Net-_M13-Pad1_ Net-_M17-Pad1_ Net-_M25-Pad2_ VDD GND Net-_M31-Pad1_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.cir.out b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.cir.out
new file mode 100644
index 000000000..179d8051a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.cir.out
@@ -0,0 +1,50 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74lvc3g17\sn74lvc3g17.cir
+
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+m4 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m9 gnd net-_m1-pad1_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m11 vdd net-_m1-pad1_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m16 net-_m13-pad1_ net-_m1-pad1_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m15 net-_m15-pad1_ net-_m1-pad1_ vdd vdd CMOSP W=100u L=100u M=1
+m21 gnd net-_m13-pad1_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m1-pad1_ net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m14 net-_m13-pad3_ net-_m1-pad1_ gnd gnd CMOSN W=100u L=100u M=1
+m23 vdd net-_m13-pad1_ net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m10-pad2_ net-_m5-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m7 net-_m10-pad3_ net-_m5-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m10 gnd net-_m10-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m5 net-_m10-pad2_ net-_m5-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m6 net-_m12-pad3_ net-_m5-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m12 vdd net-_m10-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m20 net-_m17-pad1_ net-_m10-pad2_ net-_m19-pad1_ vdd CMOSP W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m10-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m22 gnd net-_m17-pad1_ net-_m19-pad1_ vdd CMOSP W=100u L=100u M=1
+m17 net-_m17-pad1_ net-_m10-pad2_ net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+m18 net-_m17-pad3_ net-_m10-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m24 vdd net-_m17-pad1_ net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+m28 net-_m25-pad1_ net-_m25-pad2_ net-_m27-pad1_ vdd CMOSP W=100u L=100u M=1
+m27 net-_m27-pad1_ net-_m25-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m29 gnd net-_m25-pad1_ net-_m27-pad1_ vdd CMOSP W=100u L=100u M=1
+m25 net-_m25-pad1_ net-_m25-pad2_ net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m26 net-_m25-pad3_ net-_m25-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m30 vdd net-_m25-pad1_ net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m34 net-_m31-pad1_ net-_m25-pad1_ net-_m33-pad1_ vdd CMOSP W=100u L=100u M=1
+m33 net-_m33-pad1_ net-_m25-pad1_ vdd vdd CMOSP W=100u L=100u M=1
+m35 gnd net-_m31-pad1_ net-_m33-pad1_ vdd CMOSP W=100u L=100u M=1
+m31 net-_m31-pad1_ net-_m25-pad1_ net-_m31-pad3_ gnd CMOSN W=100u L=100u M=1
+m32 net-_m31-pad3_ net-_m25-pad1_ gnd gnd CMOSN W=100u L=100u M=1
+m36 vdd net-_m31-pad1_ net-_m31-pad3_ gnd CMOSN W=100u L=100u M=1
+* u1  net-_m1-pad2_ net-_m5-pad2_ net-_m13-pad1_ net-_m17-pad1_ net-_m25-pad2_ vdd gnd net-_m31-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.pro b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.sch b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.sch
new file mode 100644
index 000000000..66d337b60
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.sch
@@ -0,0 +1,899 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74LVC3G17-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+F 3 "" H 7100 2100 60  0000 C CNN
+	1    7050 2100
+	1    0    0    1   
+$EndComp
+$Comp
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+P 7800 2550
+F 0 "M29" H 7750 2600 50  0000 R CNN
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+F 2 "" H 8050 2650 29  0000 C CNN
+F 3 "" H 7850 2550 60  0000 C CNN
+	1    7800 2550
+	0    1    -1   0   
+$EndComp
+$Comp
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+U 1 1 697C70AD
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+F 0 "M25" H 7000 3050 50  0000 R CNN
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+F 2 "" H 7300 2900 29  0000 C CNN
+F 3 "" H 7100 3000 60  0000 C CNN
+	1    7000 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M26
+U 1 1 697C70AE
+P 7000 3800
+F 0 "M26" H 7000 3650 50  0000 R CNN
+F 1 "eSim_MOS_N" H 7100 3750 50  0000 R CNN
+F 2 "" H 7300 3500 29  0000 C CNN
+F 3 "" H 7100 3600 60  0000 C CNN
+	1    7000 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M30
+U 1 1 697C70AF
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+F 0 "M30" H 8000 3350 50  0000 R CNN
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+F 2 "" H 8300 3200 29  0000 C CNN
+F 3 "" H 8100 3300 60  0000 C CNN
+	1    8000 3500
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	6900 2100 6900 4000
+Connection ~ 6900 2700
+Connection ~ 6900 3400
+Wire Wire Line
+	7200 2300 7200 2500
+Wire Wire Line
+	7200 2900 7200 3200
+Wire Wire Line
+	7200 3600 7200 3800
+Wire Wire Line
+	7300 1950 7300 1900
+Wire Wire Line
+	7200 1900 7350 1900
+Wire Wire Line
+	7300 2550 7350 2550
+Wire Wire Line
+	7350 2550 7350 1900
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+Wire Wire Line
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+Wire Wire Line
+	7200 4200 7350 4200
+Wire Wire Line
+	7300 3550 7350 3550
+Wire Wire Line
+	7350 3550 7350 4200
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+Wire Wire Line
+	7600 2400 7200 2400
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+Wire Wire Line
+	7600 3700 7200 3700
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+Wire Wire Line
+	7650 2300 7350 2300
+Connection ~ 7350 2300
+Wire Wire Line
+	7650 3800 7350 3800
+Connection ~ 7350 3800
+Wire Wire Line
+	7200 3050 7800 3050
+Wire Wire Line
+	7800 2700 7800 3400
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+Connection ~ 7800 3050
+Wire Wire Line
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+Connection ~ 6900 2950
+Wire Wire Line
+	7800 2950 9300 2950
+Connection ~ 7800 2950
+Text GLabel 7350 1950 2    60   Input ~ 0
+VDD
+$Comp
+L eSim_MOS_P M34
+U 1 1 697C70B5
+P 9450 2700
+F 0 "M34" H 9400 2750 50  0000 R CNN
+F 1 "eSim_MOS_P" H 9500 2850 50  0000 R CNN
+F 2 "" H 9700 2800 29  0000 C CNN
+F 3 "" H 9500 2700 60  0000 C CNN
+	1    9450 2700
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_MOS_P M33
+U 1 1 697C70B6
+P 9450 2100
+F 0 "M33" H 9400 2150 50  0000 R CNN
+F 1 "eSim_MOS_P" H 9500 2250 50  0000 R CNN
+F 2 "" H 9700 2200 29  0000 C CNN
+F 3 "" H 9500 2100 60  0000 C CNN
+	1    9450 2100
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_MOS_P M35
+U 1 1 697C70B7
+P 10200 2550
+F 0 "M35" H 10150 2600 50  0000 R CNN
+F 1 "eSim_MOS_P" H 10250 2700 50  0000 R CNN
+F 2 "" H 10450 2650 29  0000 C CNN
+F 3 "" H 10250 2550 60  0000 C CNN
+	1    10200 2550
+	0    1    -1   0   
+$EndComp
+$Comp
+L eSim_MOS_N M31
+U 1 1 697C70B8
+P 9400 3200
+F 0 "M31" H 9400 3050 50  0000 R CNN
+F 1 "eSim_MOS_N" H 9500 3150 50  0000 R CNN
+F 2 "" H 9700 2900 29  0000 C CNN
+F 3 "" H 9500 3000 60  0000 C CNN
+	1    9400 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M32
+U 1 1 697C70B9
+P 9400 3800
+F 0 "M32" H 9400 3650 50  0000 R CNN
+F 1 "eSim_MOS_N" H 9500 3750 50  0000 R CNN
+F 2 "" H 9700 3500 29  0000 C CNN
+F 3 "" H 9500 3600 60  0000 C CNN
+	1    9400 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M36
+U 1 1 697C70BA
+P 10400 3500
+F 0 "M36" H 10400 3350 50  0000 R CNN
+F 1 "eSim_MOS_N" H 10500 3450 50  0000 R CNN
+F 2 "" H 10700 3200 29  0000 C CNN
+F 3 "" H 10500 3300 60  0000 C CNN
+	1    10400 3500
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	9300 2100 9300 4000
+Connection ~ 9300 2700
+Connection ~ 9300 3400
+Wire Wire Line
+	9600 2300 9600 2500
+Wire Wire Line
+	9600 2900 9600 3200
+Wire Wire Line
+	9600 3600 9600 3800
+Wire Wire Line
+	9700 1950 9700 1900
+Wire Wire Line
+	9600 1900 9750 1900
+Wire Wire Line
+	9700 2550 9750 2550
+Wire Wire Line
+	9750 2550 9750 1900
+Connection ~ 9700 1900
+Wire Wire Line
+	9700 4150 9700 4200
+Wire Wire Line
+	9600 4200 9750 4200
+Wire Wire Line
+	9700 3550 9750 3550
+Wire Wire Line
+	9750 3550 9750 4200
+Connection ~ 9700 4200
+Wire Wire Line
+	10000 2400 9600 2400
+Connection ~ 9600 2400
+Wire Wire Line
+	10000 3700 9600 3700
+Connection ~ 9600 3700
+Wire Wire Line
+	10050 2300 9750 2300
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+Wire Wire Line
+	10050 3800 9750 3800
+Connection ~ 9750 3800
+Wire Wire Line
+	9600 3050 10200 3050
+Wire Wire Line
+	10200 2700 10200 3400
+Connection ~ 9600 3050
+Connection ~ 10200 3050
+Wire Wire Line
+	10400 2400 10500 2400
+Text GLabel 10400 3700 2    60   Input ~ 0
+VDD
+Connection ~ 9300 2950
+Connection ~ 10200 2950
+Text GLabel 9750 1950 2    60   Input ~ 0
+VDD
+$Comp
+L PORT U1
+U 1 1 697C72FD
+P 1500 1750
+F 0 "U1" H 1550 1850 30  0000 C CNN
+F 1 "PORT" H 1500 1750 30  0000 C CNN
+F 2 "" H 1500 1750 60  0000 C CNN
+F 3 "" H 1500 1750 60  0000 C CNN
+	1    1500 1750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 697C870C
+P 1550 4600
+F 0 "U1" H 1600 4700 30  0000 C CNN
+F 1 "PORT" H 1550 4600 30  0000 C CNN
+F 2 "" H 1550 4600 60  0000 C CNN
+F 3 "" H 1550 4600 60  0000 C CNN
+	2    1550 4600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 697CA01B
+P 6650 2950
+F 0 "U1" H 6700 3050 30  0000 C CNN
+F 1 "PORT" H 6650 2950 30  0000 C CNN
+F 2 "" H 6650 2950 60  0000 C CNN
+F 3 "" H 6650 2950 60  0000 C CNN
+	5    6650 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 697CA084
+P 5300 1750
+F 0 "U1" H 5350 1850 30  0000 C CNN
+F 1 "PORT" H 5300 1750 30  0000 C CNN
+F 2 "" H 5300 1750 60  0000 C CNN
+F 3 "" H 5300 1750 60  0000 C CNN
+	3    5300 1750
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 697CA0F5
+P 5350 4600
+F 0 "U1" H 5400 4700 30  0000 C CNN
+F 1 "PORT" H 5350 4600 30  0000 C CNN
+F 2 "" H 5350 4600 60  0000 C CNN
+F 3 "" H 5350 4600 60  0000 C CNN
+	4    5350 4600
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 697CA15C
+P 10450 2950
+F 0 "U1" H 10500 3050 30  0000 C CNN
+F 1 "PORT" H 10450 2950 30  0000 C CNN
+F 2 "" H 10450 2950 60  0000 C CNN
+F 3 "" H 10450 2950 60  0000 C CNN
+	8    10450 2950
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 697CA596
+P 7700 950
+F 0 "U1" H 7750 1050 30  0000 C CNN
+F 1 "PORT" H 7700 950 30  0000 C CNN
+F 2 "" H 7700 950 60  0000 C CNN
+F 3 "" H 7700 950 60  0000 C CNN
+	6    7700 950 
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 697CA645
+P 9100 1000
+F 0 "U1" H 9150 1100 30  0000 C CNN
+F 1 "PORT" H 9100 1000 30  0000 C CNN
+F 2 "" H 9100 1000 60  0000 C CNN
+F 3 "" H 9100 1000 60  0000 C CNN
+	7    9100 1000
+	1    0    0    -1  
+$EndComp
+Text GLabel 7950 950  2    60   Input ~ 0
+VDD
+Text GLabel 9350 1000 2    60   Input ~ 0
+GND
+Text GLabel 2100 5850 0    60   Input ~ 0
+GND
+Text GLabel 5400 4050 0    60   Input ~ 0
+GND
+Text GLabel 4500 5850 0    60   Input ~ 0
+GND
+Text GLabel 3000 4050 0    60   Input ~ 0
+GND
+Text GLabel 2050 3000 0    60   Input ~ 0
+GND
+Text GLabel 2950 1200 0    60   Input ~ 0
+GND
+Text GLabel 5350 1200 0    60   Input ~ 0
+GND
+Text GLabel 4450 3000 0    60   Input ~ 0
+GND
+Text GLabel 7200 4200 0    60   Input ~ 0
+GND
+Text GLabel 9600 4200 0    60   Input ~ 0
+GND
+Text GLabel 10500 2400 0    60   Input ~ 0
+GND
+Text GLabel 8100 2400 0    60   Input ~ 0
+GND
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.sub b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.sub
new file mode 100644
index 000000000..a76041b7f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17.sub
@@ -0,0 +1,44 @@
+* Subcircuit SN74LVC3G17
+.subckt SN74LVC3G17 net-_m1-pad2_ net-_m5-pad2_ net-_m13-pad1_ net-_m17-pad1_ net-_m25-pad2_ vdd gnd net-_m31-pad1_ 
+* c:\fossee\esim\library\subcircuitlibrary\sn74lvc3g17\sn74lvc3g17.cir
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+m4 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m9 gnd net-_m1-pad1_ net-_m3-pad1_ vdd CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m2 net-_m1-pad3_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m11 vdd net-_m1-pad1_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1
+m16 net-_m13-pad1_ net-_m1-pad1_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m15 net-_m15-pad1_ net-_m1-pad1_ vdd vdd CMOSP W=100u L=100u M=1
+m21 gnd net-_m13-pad1_ net-_m15-pad1_ vdd CMOSP W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m1-pad1_ net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m14 net-_m13-pad3_ net-_m1-pad1_ gnd gnd CMOSN W=100u L=100u M=1
+m23 vdd net-_m13-pad1_ net-_m13-pad3_ gnd CMOSN W=100u L=100u M=1
+m8 net-_m10-pad2_ net-_m5-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m7 net-_m10-pad3_ net-_m5-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m10 gnd net-_m10-pad2_ net-_m10-pad3_ vdd CMOSP W=100u L=100u M=1
+m5 net-_m10-pad2_ net-_m5-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m6 net-_m12-pad3_ net-_m5-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m12 vdd net-_m10-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1
+m20 net-_m17-pad1_ net-_m10-pad2_ net-_m19-pad1_ vdd CMOSP W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m10-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m22 gnd net-_m17-pad1_ net-_m19-pad1_ vdd CMOSP W=100u L=100u M=1
+m17 net-_m17-pad1_ net-_m10-pad2_ net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+m18 net-_m17-pad3_ net-_m10-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m24 vdd net-_m17-pad1_ net-_m17-pad3_ gnd CMOSN W=100u L=100u M=1
+m28 net-_m25-pad1_ net-_m25-pad2_ net-_m27-pad1_ vdd CMOSP W=100u L=100u M=1
+m27 net-_m27-pad1_ net-_m25-pad2_ vdd vdd CMOSP W=100u L=100u M=1
+m29 gnd net-_m25-pad1_ net-_m27-pad1_ vdd CMOSP W=100u L=100u M=1
+m25 net-_m25-pad1_ net-_m25-pad2_ net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m26 net-_m25-pad3_ net-_m25-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m30 vdd net-_m25-pad1_ net-_m25-pad3_ gnd CMOSN W=100u L=100u M=1
+m34 net-_m31-pad1_ net-_m25-pad1_ net-_m33-pad1_ vdd CMOSP W=100u L=100u M=1
+m33 net-_m33-pad1_ net-_m25-pad1_ vdd vdd CMOSP W=100u L=100u M=1
+m35 gnd net-_m31-pad1_ net-_m33-pad1_ vdd CMOSP W=100u L=100u M=1
+m31 net-_m31-pad1_ net-_m25-pad1_ net-_m31-pad3_ gnd CMOSN W=100u L=100u M=1
+m32 net-_m31-pad3_ net-_m25-pad1_ gnd gnd CMOSN W=100u L=100u M=1
+m36 vdd net-_m31-pad1_ net-_m31-pad3_ gnd CMOSN W=100u L=100u M=1
+* Control Statements
+
+.ends SN74LVC3G17
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17_Previous_Values.xml b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17_Previous_Values.xml
new file mode 100644
index 000000000..dc25ea5b8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/SN74LVC3G17_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model /><devicemodel><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m9><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m11><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m16><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m15><m21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m21><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m13><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m14><m23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m23><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m8><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m7><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m10><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m12><m20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m20><m19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m19><m22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m22><m17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m17><m18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m18><m24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m24><m28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m28><m27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m27><m29><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m29><m25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m25><m26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m26><m30><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m30><m34><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m34><m33><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m33><m35><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m35><m31><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m31><m32><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m32><m36><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m36></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC3G17/analysis b/library/SubcircuitLibrary/SN74LVC3G17/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC3G17/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file