Name		Name	Last commit message	Last commit date
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FPGA		FPGA
Logisim		Logisim
Picture		Picture
README.md		README.md
课程设计指南V1.9.pdf		课程设计指南V1.9.pdf

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MIPS 五段流水CPU

A MIPS CPU with pipeline, and tested with a MIPS benchmark , implements multiple interupt and BHT and etc.

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