We are a research group from the Department of Computer Engineering, University of Peradeniya, exploring neuromorphic and next-generation computing inspired by the brain. Our projects focus on advancing energy-efficient and adaptive computing systems
For any inquiry, please contact Dr. Isuru Nawinne or Prof. Roshan Ragel
A robust, automated SRAM compiler workflow based on OpenRAM. Features fixes for modern Python/Numpy environments, automated multi-bank generation, and Synopsys (DB/NDM) post-processing.
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
This project implements a neuromorphic Network-on-Chip using customized RV32IMF RISC-V cores, a 2D mesh NoC, and neuron bank hardware to accelerate spiking neural networks. It supports event-driven spike communication via custom ISA extensions and AXI interfaces, and is implemented and tested on an FPGA.
This project implements a neuromorphic NoC using RISC-V nodes with custom hardware to simulate spiking neural networks. Tested on an FPGA, it supports up to 1,024 neurons and uses dedicated FIFO buffers for stable, low-power operation. The design combines RISC-V flexibility with hardware acceleration for efficient small-scale SNN applications.
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
This project implements a neuromorphic architecture using parallel RISC-V processing elements to model spiking neurons, either individually or virtually grouped. It will also develop encoder and decoder modules to benchmark the system on classical machine learning tasks.
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