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Add ec_rgb_kb_color CFR option to select RGB keyboard color at boot. Suppress regular keyboard backlight option when RGB keyboard is present, as they are mutually exclusive. TEST=build/boot google/mithrax, verify RGB keyboard option enabled, all colors able to be set at boot. Change-Id: I55848931248a70023c49b98190105679f2999ad9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Enable SMBIOS Processor Upgrade Type reporting for Socket BGA1744.
- Add CPU_INTEL_SOCKET_BGA1744 Kconfig option
- Add socket_BGA1744 subdirectory to build system
- Map to PROCESSOR_UPGRADE_SOCKET_BGA1744 in SMBIOS Type 4
TEST=Built for mc_rpl1, verified `dmidecode -t processor | grep Upgrade`
shows "Socket BGA1744"
Change-Id: I18123f8ab656d4ca8c540be402f47929f8550ede
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89899
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Move the sensor SSDB struct and enums out of `chip.h` and into a new `ssdb.h`. This keeps the chip interface header lean while providing a dedicated spot for the additional SSDB field descriptors coming in follow-up changes. No functional impact. Change-Id: Ifb2dddb886f0123b1dfd059400dcacd75174fb6c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90181 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reflow the multiline comments in `ssdb.h` to 100 columns. While this slightly exceeds the 96 column recommended limit in the coding style guide, the overall effect improves rather than reduces readability. Change-Id: I5b98d48ea5a99e38eb3472dfd24be434433857cc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add a static assert ensuring `struct ssdb` stays 0x6C bytes, matching the sensor descriptor in ACPI. This guards future edits from drifting away from the documented layout without changing runtime behavior. Change-Id: I2b4dfb86494d13525cbc6e6de4573ceb36f0b482 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90183 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename `intel_camera_platform_type` to `platform_type` and populate it using the available values from the Intel Camera DDK available on Windows Update and slimbootloader. Change-Id: I7c40e29dbf71caf7b655e8f2e5b4be7cc6970194 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90184 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Retitle the SSDB flash-support enum to `flash_support`, aligning its name with the field in the struct and the spec. Also keep the existing values and clarify the default case comment. Change-Id: I49d825cb44d7f8784350e29e8b2b5a0772549f56 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90185 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce `platform_subtype` constants for the SSDB `platform_sub` field, matching the legacy FFD/CHT1/CHT2 values plus an unknown default. Change-Id: Ib705252b089d161a7addc372d05e5062307bfb21 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Introduce enums covering the SSDB ROM/VCM types, orientation, control logic, camera position, voltage rails, PHY config, MCLK source, SKU vendor, and SKU card type fields, plus a packed helper for the SKU bitfield. This replaces magic values with named constants ahead of further SSDB work without changing behaviour. Change-Id: Iacc1a844528e2427c9f4ca8fcebe338fb6c1bac4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90187 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch the `sensor_card_sku` field in `struct intel_ssdb` from a raw byte to the new `sensor_sku_info` bitfield wrapper so callers can access the vendor/card type flags symbolically. Field size stays the same, so layout and behavior are unchanged. Change-Id: I85ecbbec1a749c07e4d83d953d47d76854447cb1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add comments for the tail of `struct intel_ssdb`, naming the camera position, voltage rail, PPR, flash, PHY, lane, and external MCLK fields instead of treating them as an opaque reserved block. Keeps the struct aligned with the ACPI blob while making each byte’s meaning explicit. Change-Id: Id9ae2bf77e901ef0f88b6f51985b59d41c5529d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove the use_pld and disable_pld_defaults flags and always generate the Physical Location Descriptor (PLD) for camera sensor devices. PLD is required for proper camera enumeration and identification in modern ACPI implementations, so making it optional was incorrect. Changes: - Remove use_pld field: PLD generation is now always enabled - Remove disable_pld_defaults field: PLD defaults are always applied - Always call apply_pld_defaults() and acpigen_write_pld() TEST=tested with rest of patch train Change-Id: Ifd408f32a4feaf9728913dd150d1cb3e7b1c3c60 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Set SSDB version and card type default values, as both fields are required by both Linux and Windows MIPI camera drivers. TEST=tested with rest of patch train Change-Id: Ia43bc61caef427a86883a6295af1606eac00229f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove the (unused) disable_ssdb_defaults field and its usage. SSDB defaults should always be applied to ensure proper camera sensor configuration. This simplifies the code and ensures consistent behavior across all camera sensor configurations. TEST=tested with rest of patch train Change-Id: I3bc00cdd28ace925b44712a17dec07f7f2b8c97a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The SSDB platform field was unset on many boards, causing the driver to default to PLAT_SKC (Skylake). This field is required for proper camera sensor initialization and is validated by the driver. Set the correct platform enum value based on the SoC. TEST=tested with rest of patch train Change-Id: I34e0aba0ba34dabcf25287ff04bc4251135ca09e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90196 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Many boards were incorrectly using the VCM I2C address (0x0C) as the SSDB vcm_type field value. These are two separate fields: - ssdb.vcm_type: Enum identifying the VCM chip model (VCM_DW9714, VCM_DW9808, etc.) used by drivers to select appropriate VCM functions - vcm_address: I2C address of the VCM device (typically 0x0C) Replace hardcoded "0x0C" values in ssdb.vcm_type with the correct enum values based on the actual VCM device: - VCM_DW9714 for boards using DW9714 VCMs - VCM_DW9808 for boards using DW9768 VCMs (DW9768 doesn't have an enum, but DW9808 has compatible register layout) Add vcm_address = "0x0C" to all affected boards to properly specify the I2C address separately from the VCM type. This ensures the Windows and Linux camera drivers receive the correct VCM type information needed for proper initialization and function pointer selection. TEST=tested with rest of patch train Change-Id: I53a560b0b03a1fe49d35ad8238679cc130327ade Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Eric Lai <ericllai@google.com>
Add BOE panel NS130069-M00 serializable data to CBFS. Datasheet: NS130069-M00_V01_20250916.pdf [INFO ] CBFS: Found 'panel-BOE_NS130069_M00' @0xfc480 size 0x68b in mcache @0xfffdd62c BUG=b:456907241 TEST=build and check the CBFS include the panel BRANCH=none Change-Id: Iefdfc7f6d8cea1d8d791e4d49ab63e78d306a6a4 Signed-off-by: Xiaokun Qiao <qiaoxiaokun@huaqin.corp-partner.google.com> Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90007 Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
The panel id is sampled with AUXADC_VIN3 (PANEL_ID_HIGH_CHANNEL)
and AUXADC_VIN4 (PANEL_ID_LOW_CHANNEL).
[DEBUG] ADC[2]: Raw value=1744 ID=7
[DEBUG] ADC[3]: Raw value=283 ID=1
[DEBUG] Panel ID: 0x9
BUG=b:448281461
TEST=build and check the CBFS include the panel ID
BRANCH=none
Change-Id: I3b010162bb5b892d528c74e2d38e624465fa90dc
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90190
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add support to reserve 33 MB DRAM memory for display in memlayout.ld file. TEST=Create an image.serial.bin and ensure it boots on X1P42100. Basic device boot functionality with the specified memory reservation has been validated. Display functionality has not yet been tested, as the display driver porting is yet to be done. Change-Id: I49a4a20b9869bc5cf0b11f4eb6cff7865bb2e761 Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90242 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cache the brightness level requested via _BCM and return it from XBQC while the IGD OpRegion registers are still zeroed during S3 resume. Once BCLM is valid we refresh the cache with the hardware reading. This keeps _BQC from reporting zero after resume. Change-Id: I3f06c9cf6529da6d634d7b0368f0c88b468f0c45 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Our 18-entry BRIG table advertised is only a handful of steps and identical AC/DC defaults, so after S3, the OS falls back to the default index if the the cached entry doesn't match. Populate BRIG with the full 0–100 ladder so every cached index corresponds to an actual entry. Change-Id: I319cf3a0ced3bf6021f9e768f0e9bb5529b12ed5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89987 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The OS replays _BCM requests while the graphics driver is still reinitializing, so hardware brightness can diverge from what we cached in BRLV. Reapply the cached level once the OpRegion is ready to keep firmware and OS state aligned. Change-Id: I2e6ed0936b2e74f55a2c760e7f4fcf56a2e02c53 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Verstage cannot use the UEFI variable store because it runs before the SMMSTORE is initialized/available, and because the required EDK2 headers are x86-specific. Provide inline stub that returns fallback values to satisfy console_init() dependency. TEST=build google/dewatt with CFR enabled Change-Id: Icaa493692006cf3e0bb194ee3fdd9caf2f51cda1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The EFI variable store driver (efivars.c) and option backend (option.c) require EDK2 headers which are x86-specific and not available in ARM verstage. Use 'all_x86-' instead of 'all-' to exclude verstage while keeping other x86 stages and SMM. TEST=build google/dewatt with CFR enabled Change-Id: I6d0955423cb55658725dfa3025b2118736f5e63b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the structs are the same, we may as well use the ones directly from the driver (since it implements the standard anyway). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I44116e5e977029c37e1bf9b9d8ce8d6c022b5b0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/89870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
renoir uses the A/B recovery flash layout without the ISH structure. But this is handled by amdfwtool. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If9d53bf8fb5fe80779af20ccf7aa3bd9d88a5cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Modify the power limit setting like below PL1 : 15 PL2 : 35 PL4 : 150 BUG=b:464422702 TEST=Build and check the system could boot to OS Change-Id: I629af9bdf41cd2344d8b4189f49a0e27f5db695d Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90246 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 4ded52b4b0e1: 2025-08-11 17:00:18 -0600 - (microcode-20250812 Release) to commit id f910b0a225d6: 2025-11-10 16:26:35 -0600 - (microcode-20251111 Release) This brings in 1 new commits: f910b0a225d6 microcode-20251111 Release Change-Id: I215558de6938c1955faff3250f791da34b97f0c4 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add Vboot configuration (Kconfig and FMDs for RO only and RW_A layouts). TEST=Build with UEFIPayload and boot to payload. Verify in cbmem logs that verstage has executed and selected Slot A in the case of RW_A layout. Change-Id: Ide2a3a4b59be5b27bf7315690520c9392a98d044 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is the MCH Strap Length, and FMSBA is the corresponding Flash MCH Strap Base Address. See ICH8 datasheet, FLMAP2. Change-Id: I322c13d9228800a2736b0288377495287521712c Signed-off-by: Daniel Maslowski <info@orangecms.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89614 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Auto-generated by util/vboot_list/vboot_list.sh. Change-Id: I0f8d5a7857a9a1ad954204481cf56f64f34ee7ca Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The Infineon SLB 9672 on newer Clevo machines regularly fails TPM Resume on S3 with the error `TPM_RC_VALUE`. Per TPM2 spec, handle the failure by performing a TPM Restart. > The startup behavior defined by this specification is different than > TPM 1.2 with respect to Startup(STATE). A TPM 1.2 device will enter > Failure Mode if no state is available when the TPM receives > Startup(STATE). This is not the case in this specification. It is up > to the CRTM to take corrective action if it the TPM returns > TPM_RC_VALUE in response to Startup(STATE). Fixes the following error from being repeatedly logged in Linux: > kernel: tpm tpm0: A TPM error (256) occurred attempting get random Ref: Trusted Platform Module Library, Part 1: Architecture, rev 1.59 Change-Id: I3388007d4448c93bd0dda591c8ca7d1a8dc5306b Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: Ic30bec272e82535f6f606033c3ba512662cb2c8b Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
These values were taken from alderlake. Change-Id: Ib790c7d52748156b25bad423ed082c1b51a33550 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
Intel introduced a new UPD specifically for setting the HDA subsystem ID in FSP-M. Using SiSsidTablePtr in FSP-S no longer works as it will be locked with a default value of 0 by that point. Tested on Clevo V560TU with MTL FSP 4122.12 (0D.00.A8.20). TEST=PCI config space for HDA device has subsystem ID set. Change-Id: I5e668747d99b955b0a3946524c5918d328b8e1d3 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15 Signed-off-by: Jeremy Soller <jeremy@system76.com>
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9 Signed-off-by: Tim Crawford <tcrawford@system76.com>
This config is not available in coreboot FSP headers, but is required for USB3 to work correctly. Change-Id: I253c7b6b9fe67e251f6ba88d8176c7058292de0a Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Bonobo has been updated with a Thunderbolt 5 controller (Barlow Ridge). Identified chip changes from the schematics: - JHL8540_MP -> JHL9580_QS - TPS65994BF -> TPS65994BH - IT5570E-128 -> IT5570E-256 Change-Id: I784e489cdd034febeaaac0182ab5b4fe672381ec Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Meerkat 9 is an Intel Meteor Lake-H based small form factor desktop computer based on the Asus NUC-155H R2. Change-Id: I37a0b808cf383379b8e284831644c824c0d4817e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I202c0607c2cdac1df59f42fb41735704dd5bd95c Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I4b07846c404eb93ab4baf0a78a4bbffcc5d8afca Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The driver provides ACPI support for dynamically powering on and off the GPU, NVIDIA Dynamic Boost support, and a function for enabling the GPU power in romstage. References: - DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide - DG-09954-001: NVIDIA GN20/QN20 Software Design Guide Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I4ca91ff631dd4badbfba72e69651f03753323a54 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add a new driver for discrete Thunderbolt controllers. This allows using e.g. Maple Ridge devices on Raptor Point PCH. Ref: Titan Ridge BIOS Implementation Guide v1.4 Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472) Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
The HX boards, using PCH-S, use a discrete Thunderbolt device (Intel Maple Ridge), as opposed to a built-in one like the boards using PCH-P. Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller. Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350 Signed-off-by: Tim Crawford <tcrawford@system76.com>
The newer batch of these boards do not de-assert VW PLTRST# on S3 resume, causes the units to not power on in the EC code. Switch them to S0ix by default, but leave S3 available. Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Since these boards will use S0ix they need to leave CSME enabled for the CPU to reach C10. Change-Id: I70c908402c9964508bb9c439d48d24773f5a35ab Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I5873e2bd61b76331ed88023260ece3ab9c3c3eff Signed-off-by: Tim Crawford <tcrawford@system76.com>
Disable feature as it causing GPU to fail under load, such as running FurMark as part of Phoronix Test Suite. Change-Id: I0b04cbd8fbab2ba8ff38281b91c83aa94c7e1bf1 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I291a806912f967fa797b5fae77c5fff6610733bf Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: Ifeec06c1c79216afe840eff2d9cb91a6d4d8d5a3 Signed-off-by: Tim Crawford <tcrawford@system76.com>
- Add more inline docs - Add `_STA` method - Update field names to better match names from Clevo dumps/DG samples - Add fields for v2.4 (unimplemented) - Add `TGPA` field for `UPDATE_DYNAMIC_PARAMS` - Match proprietary behavior for "Set Controller Status" - Add objects for disabling boost on AC/DC - Add debug logs for unimplemented functions Change-Id: I2a8d791198e18fca6eb907e62f92143fbe1e3962 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I9e5525d4197953c430325d813ee20d980dddab63 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
Change-Id: Iea09f90a6e53035ce379afa6d7dd4ad3a83333c6 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
Change-Id: Iafb7d137332ee0668dfc1a3cf47a4d881b8cdfb8 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
Change-Id: I5f0b8cf65446b275deb5207d344fde97da1dc833 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Fixes: c0ba116 ("soc/intel/adl,mtl: Use channel 0 only for memory down in mixed topo") Change-Id: I56e7d51b4a06519376d8fe7a345bb434c6f1a24a Signed-off-by: Tim Crawford <tcrawford@system76.com>
The GPU sometimes crashes when GPU Boost is used. Disable the feature until root cause can be identified and resolved. Change-Id: Ib3624c1241921268627cfc85b4427bc9891fa0a3 Signed-off-by: Tim Crawford <tcrawford@system76.com>
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