VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…

RTL Design Using Verilog with SKY130nm Technology

Physical Design of Mixed signal circuit that performs- "In Memory logic using 8TSRAM cells" using OPENFASOC.

Physical Design of Mixed Signal Circuit that performs - "Post-Layout: OpenFASOC flow for 3-bit Flash ADC using TIQ comparator".

This repository contains Verilog and UVM-based design and verification files for a sequence detector (110), organized with support files for simulation, testing, and reporting.

Complete RTL-to-GDSII implementation of the PicoRV32 RISC-V core using Cadence Xcelium, Genus, Innovus and Tempus (180nm) with 100MHz timing closure.

Developed and integrated hard macros for RISC-V processor sub-modules, optimizing for area, power, and performance. Executed complete physical design flow, including synthesis, floor planning, placement, routing, and static timing analysis, targeting a 32nm technology node.

Database implementation for boutique.

Step-by-step documented flow for performing ASIC design using OpenROAD. Includes environment setup, floorplanning, placement, routing, and timing closure — with verified commands and tool versions.

This Repo is to demonstrate RTL to GDSII design implementation

A fully custom CMOS inverter designed using SKY130 open-source PDK, covering the schematic-to-layout flow. The design uses Xschem for schematic capture, Magic VLSI for layout, and ngspice for DC, transient, delay, and power analysis. Physical verification is performed using DRC and LVS with Magic and Netgen to ensure schematic–layout consistency.